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publication# 19574 rev. a amendment /0 issue date: april 1995 this document contains information on a product under development at advanced micro devices, inc. the information is intended to help you to evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. advanced micro devices am79c850 supernet a 3 preliminary distinctive characteristics n compliant with the ansi x3t9.5/iso 9314 specification 100 mbps data rate timed token-passing protocol ring topology n complete memory management supports 256k bytes of local frame buffer memory supports buffer memory bandwidths of 200 mbps and 400 mbps tag-mode: minimum latency/highest performance buffer memory management, ideal for adapter card designs n ansi-compliant tp-pmd stream cipher scrambling/descrambling n full duplex operation: 200 mbps continuous data rate n supports both fiber optic and copper twisted- pair media n diagnostic features built in self test (bist) in address filter, physical layer controller with scrambler n hardware physical connection management support n low power consumptionreduction of more than 25% from supernet 2 solution functional overview supernet 3 is a 208-pin cmos integration of fddi mac, phy, address filter, and clock generation and recovery functions. it is the third generation fddi offering from amd which integrates the supernet 2 family of chips into a single-chip solution. refer to the supernet 2 data book (pid 15502c) for basic feature descriptions. the supernet 3 is backward compatible to the supernet 2 tag mode of operation in which the supernet 3 buffer memory interface logic maintains the buffer memory as multiple fifos. the supernet 3 provides dma channels, arbitrates access to the network buffer memory, and controls the data path between the buffer memory and the medium. the mac also implements the timed-token protocol and receive/transmit control as specified for the media access control (mac) sublayer of the iso standard 9314-2 for fddi. the physical layer functions defined by the iso 9314-1 are performed by the supernet 3. supernet 3 implements on-chip digital clock recovery and transmit functions for fiber. to support copper media, the phy-pmd interface is maintained and an external module can be implemented in the same footprint as the fiber optic transceiver to perform the mlt-3 encoding/decoding and equaliza- tion. supernet 3 integrates the scrambler and descrambler functions for transmissions over copper media. supernet 3 features update the basic feature description for supernet 3 is provided in the supernet 2 data book. the enhanced features are as listed below: n this is a cmos integration of the redesigned formac plus, an enhanced plc, a 32-entry address filter (af, which is based on a content addressable memory, or cam, core), and a cmos pdx core for clock and data recovery. n a 32-entry, extensible and fully maskable af allows additional individual and group addresses to be supported. n the physical data transmitter and receiver (pdx) circuits are also embedded on-chip using proprietary digital clock-recovery technology. n for the purposes of implementing copper pmd, the scrambler/descrambler functions are embedded within the chip. n the buffer memory interface has been modified to support slower srams (35 ns) without affecting backward compatibility with supernet 2. n supernet 3 supports the fddi single attachment station (sas) but is capable of supporting a dual attachment station (das)
amd p r e l i m i n a r y 2 supernet 3 configurations with an external physical layer controller. n supernet 3 has a test access port and boundary scan architecture, ieee1149.1. n supernet 3 provides built-in self test (bist) features for the address filter, and plc-s. n all registers are readable and writable by the node processor. all reserved bits shall be read back as zero except where noted. n the receive status (rs) pins are expanded from 5 to 6 pins to support enhanced status reporting. n the transmit status (xs) pins are expanded from 3 to 4 pins to support enhanced status reporting. n enhanced frame reception is possible by splitting the receive queue. n modified tag mode of operation for easy conversion from non-tag supernet 2 to supernet 3. n all supernet 3 registers will be initialized with a default value on reset. n the a, c indicator setting has been modified. it is now possible to control the setting of the a, c indicators independent of the mode of operation (online, online special mode, and external loopback mode). n maskable vectored-interrupts are provided. it is now possible to detect the event causing the interrupt in the supernet 3 in two cycles by reading the vector register which gives the vector of the status register followed by a read of the appropriate status register. n an additional mode register (mdreg3) is provided. setting the bits in this mode register enables the additional supernet 3 features.
p r e l i m i n a r y amd 3 supernet 3 block diagram npmemreq npmemack hsreq hsack rdata1 qctrl addr bd bdp bdtag cso rd, wr flxi rs xs rdata2 tx npaddr ds cs r/ w ready mintr rst npmode lsclk bmclk node processor interface enhanced f+ enhanced plc with scrambler descrambler digital xmitter/ receiver (pdx) clock logic das/sas control & mux address filter tap controller rbus rx 16 8 npdata 4 3 3 16 32 4 2 6 4 10 10 tbus 10 10 match status control rxint 8 8 4 xsa_xact xsamat xda_xact trst rxafl[3:0] rxafu[3:0] rxafcu rxafcl 4 4 xdamat tms tck tdo tdi npcontrol npdata npaddr 6 16 8 bclk xpar x xcu, xcl r rcu, rcl rpar lsr ulsb ebferr fotoff encoff tx+ tx- rx+ rx- sdi+ sdi- scrm tdat lpbck rdat 5 5 8 2 8 2 3
amd p r e l i m i n a r y 4 supernet 3 table of contents distinctive characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional overview 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supernet 3 features update 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . connection diagram 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin description 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supernet 2 features not supported 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . miscellaneous changes from supernet 2 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . explanation of enhancements 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . status pins 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . slower buffer memory interface 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clocking 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a, c indicators 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit queues 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . non-tag mode of operation no longer supported 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . modified tag mode operation 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit command 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tdat loopback 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mode register 3 (mdreg3) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address space 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupts 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive flush/transmit inhibit pin flxi (input) 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . single frame receive mode 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive queue operation 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address bit swapping 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . auto-unlocking of receive queues 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . symbol control 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dual attachment station (das) support 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . changes and enhancements to phy 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . testability 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . summary of changes to status and mode registers 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . status register 3 (st3u & st3l) 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . parity generation and checking 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . node processor synchronous mode operation 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address filter (af) support 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . introduction 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . function of the address filter 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . node processor registers 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mac interface 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
p r e l i m i n a r y amd 5 supernet 3 table of contents (continued) address filter test specification 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . introduction 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . test logic description 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . writing entries into the af 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . finding entries in the af 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . invalidating entries in the af 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pdx functional description 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . introduction 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . default timer and register values 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supernet 3 registers 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supernet 3 programmable registers 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supernet 3 command registers 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supernet 3 command registers 1 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supernet 3 command registers 2 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision i.d. 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc characteristics over operating ranges unless otherwise specified 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching characteristics over commercial operating ranges 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . references 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phy device 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mac device 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . testability 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . physical dimensions 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pqr208, trimmed and formed 208-pin plastic quad flat pack (measured in inches) 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
amd p r e l i m i n a r y 6 supernet 3 list of figures figure 1. memory receive queue (modified tag mode) 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 2. register 3 (mdreg3) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 3. frame selection register (frselreg) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 4. delay register (unlckdly) 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 5. thru_a configuration 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 6. wrap_a configuration 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 7. wrap_b configuration 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 8. wrap_s or sas configuration 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 9. status register 1 C upper 16 bits (st1u) (npaddr = 00h) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 10. status register 1 C lower 16 bits (st1l) (npaddr = 01h) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 11. status register 2 C upper 16 bits (st2u) (npaddr = 02h) 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 12. status register 2 C lower 16 bits (st2l) (npaddr = 03h) 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 13. mode register 1 (mdreg1) (npaddr = 10h) 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 14. mode register 2 (mdreg2) (npaddr = 20h) 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 15. status register 3 C upper 16 bits (st3u) (npaddr = 61h) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 16. status register 3 C lower 16 bits (st3l) (npaddr = 62h) 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 17. buffer memory queue organization 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 18. command register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 19. command register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 20. node processor comparand register (afcomp2) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 21. node processor comparand register (afcomp1) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 22. node processor comparand register (afcomp0) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 23. mask register (afmask2) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 24. mask register (afmask1) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 25. mask register (afmask0) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 26. personality register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 27. af-mac interface handshake 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 28. clock timings 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 29. np asynchronous read 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 30. np asynchronous write 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 31. np synchronous read and write except mdr accesses 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 32. np synchronous read and write mdr accesses 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 33. host interface signal timings 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 34. np dma signals 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 35. host interface signal timings 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 36. buffer memory read cycle timings 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 37. buffer memory write cycle timings 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 38. phy interface timings 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 39. mac miscellaneous signal timings 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 40. external cam interface timings 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 41. phy miscellaneous signal timings 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 42. test interface signal timings 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 43. pmd interface signal timings 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
p r e l i m i n a r y amd 7 supernet 3 connection diagram 208-pin pqr (top view) 180 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 163 162 161 160 159 158 190 189 188 187 186 185 184 183 182 181 179 178 177 175 174 176 173 172 171 170 169 168 167 165 164 166 157 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 56 57 58 59 60 61 62 98 99 100 101 102 103 104 54 55 53 145 132 131 130 129 128 127 126 125 124 123 122 156 155 154 153 152 151 150 149 148 147 146 144 143 142 141 140 139 138 137 136 135 134 133 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 31 42 43 44 45 46 47 48 49 50 51 52 4 5 6 7 8 9 10 11 1 2 3 28 29 30 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 40 41 32 33 34 35 36 37 38 39 v sso np[15] np[14] np[13] np[12] np[11] np[10] v cco np[9] np[8] np[7] v sso np[6] np[5] np[4] np[3] np[2] np[1] np[0] v sso mintr1 mintr2 mintr3 mintr4 bmclk v ss bclk v cc npmemrq npmemack v ss ready r/ w ds csi lsclk npa[7] npa[6] npa[5] npa[4] npa[3] npa[2] npa[1] npa[0] npmode rst trst tck tms tdi tdo v ccp v sso addr[15] addr[14] addr[13] addr[12] v sso addr[11] addr[10] addr[9] addr[8] v cco addr[7] addr[6] addr[5] addr[4] v sso addr[3] addr[2] addr[1] addr[0] v sso qctrl[0] qctrl[1] qctrl[2] v cc hsack hsreq[0] hsreq[1] hsreq[2] rdata1 rdata2 v cco bd[0] bd[1] bd[2] bd[3] v sso bd[4] bd[5] bd[6] bd[7] v sso bd[8] bd[9] bd[10] bd[11] bd[12] bd[13] bd[14] bd[15] rd v cco v sso wr cso bd[16] bd[17] bd[18] bd[19] v cco bd[20] bd[21] bd[22] bd[23] v sso bd[24] bd[25] v ss bd[26] bd[27] bd[28] v cc bd[29] bd[30] bd[31] bdp[3] v sso bdp[2] bdp[1] bdp[0] bdtag v sso rxafl[0] rxafl[1] rxafl[2] rxafl[3] rxafu[0] rxafu[1] rxafu[2] v ss rxafu[3] rxafcl rxafcu v cc xdamat xda_xact xsamat xsa_xact v cc rs[5] rs[4] rs[3] rs[2] v cco v ssp scrm encoff ebferr v ssd v ccd tx+ tx- v cce v sse rx- rx+ sdi- sdi+ fotoff ulsb lsr[2] lsr[1] lsr[0] rpar r[0] r[1] r[2] v ss r[3] r[4] r[5] r[6] r[7] rcl rcu flxi v sso xpar x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] xcl scu v ss xs[0] xs[1] xs[2] xs[3] rs[0] rs[1] v cco 19574a-1
amd p r e l i m i n a r y 8 supernet 3 pqfp pin designations listed by pin number pin # description 1 vsso 2 np[15] 3 np[14] 4 np[13] 5 np[12] 6 np[11] 7 np[10] 8 vcco 9 np[9] 10 np[8] 11 np[7] 12 vsso 13 np[6] 14 np[5] 15 np[4] 16 np[3] 17 np[2] 18 np[1] 19 np[0] 20 vsso 21 mintr1 22 mintr2 23 mintr3 24 mintr4 25 bmclk 26 vss 27 bclk 28 vcc 29 npmemrq 30 npmemack 31 vss 32 ready 33 r/ w 34 ds pin # description 35 csi 36 lsclk 37 npa[7] 38 npa[6] 39 npa[5] 40 npa[4] 41 npa[3] 42 npa[2] 43 npa[1] 44 npa[0] 45 npmode 46 rst 47 trst 48 tck 49 tms 50 tdi 51 tdo 52 vccp 53 vssp 54 scrm 55 encoff 56 ebferr 57 vssd 58 vccd 59 tx+ 60 txC 61 vcce 62 vsse 63 rxC 64 rx+ 65 sdiC 66 sdi+ 67 fotoff 68 ulsb pin # description 103 rs[1] 104 vcco 105 vcco 106 rs[2] 107 rs[3] 108 rs[4] 109 rs[5] 110 vcc 111 xsa _ xact 112 xsamat 113 xda _ xact 114 xdamat 115 vcc 116 rxafcu 117 rxafcl 118 rxafu[3] 119 vss 120 rxafu[2] 121 rxafu[1] 122 rxafu[0] 123 rxafl[3] 124 rxafl[2] 125 rxafl[1] 126 rxafl[0] 127 vsso 128 bdtag 129 bdp[0] 130 bdp[1] 131 bdp[2] 132 vsso 133 bdp[3] 134 bd[31] 135 bd[30] 136 bd[29] pin # description 69 lsr[2] 70 lsr[1] 71 lsr[0] 72 rpar 73 r[0] 74 r[1] 75 r[2] 76 vss 77 r[3] 78 r[4] 79 r[5] 80 r[6] 81 r[7] 82 rcl 83 rcu 84 flxi 85 vsso 86 xpar 87 x[0] 88 x[1] 89 x[2] 90 x[3] 91 x[4] 92 x[5] 93 x[6] 94 x[7] 95 xcl 96 xcu 97 vss 98 xs[0] 99 xs[1] 100 xs[2] 101 xs[3] 102 rs[0]
p r e l i m i n a r y amd 9 supernet 3 pqfp pin designations listed by pin number pin # description 137 vcc 138 bd[28] 139 bd[27] 140 bd[26] 141 vss 142 bd[25] 143 bd[24] 144 vsso 145 bd[23] 146 bd[22] 147 bd[21] 148 bd[20] 149 vcco 150 bd[19] 151 bd[18] 152 bd[17] 153 bd[16] 154 cso pin # description 155 wr 156 vsso 157 vcco 158 rd 159 bd[15] 160 bd[14] 161 bd[13] 162 bd[12] 163 bd[11] 164 bd[10] 165 bd[9] 166 bd[8] 167 vsso 168 bd[7] 169 bd[6] 170 bd[5] 171 bd[4] 172 vsso pin # description 173 bd[3] 174 bd[2] 175 bd[1] 176 bd[0] 177 vcco 178 rdata2 179 rdata1 180 hsreq[2] 181 hsreq[1] 182 hsreq[0] 183 hsack 184 vcc 185 qctrl[2] 186 qctrl[1] 187 qctrl[0] 188 vsso 189 addr[0] 190 addr[1] pin # description 191 addr[2] 192 addr[3] 193 vsso 194 addr[4] 195 addr[5] 196 addr[6] 197 addr[7] 198 vcco 199 addr[8] 200 addr[9] 201 addr[10] 202 addr[11] 203 vsso 204 addr[12] 205 addr[13] 206 addr[14] 207 addr[15] 208 vsso
amd p r e l i m i n a r y 10 supernet 3 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: temperature range c = commercial (0 c to +70 c) package type k = plastic quad flat pack in tapepak (pqr208) speed option not applicable device number/description am79c850 supernet 3 am79c850 valid combinations kc, kc\w valid combinations alternate packaging option \w = trimmed and formed in a tray (pqj208) am79c850 k c \w valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. optional processing blank = standard processing
p r e l i m i n a r y amd 11 supernet 3 pin description i/o pins can only be high impedance in test access port (tap) operation. refer to tap testability section. phy/pmd interface (46 pins) rx+, rx- receive data (pecl input) these pins receive differential nrzi data. tx+, tx- transmit data (pecl output) these transmit outputs carry differential nrzi data. they can be forced to logical 0 (tx+ low, tx- high) by asserting the fotoff input. rcu receive control upper (ttl input) rcu is asserted high to indicate that the upper nibble of the r bus (r7C4) is a network control character. when rcu is low, this nibble contains data. rcu is synchro- nous to bclk. this pin has internal pull-up. rcl receive control lower (ttl input) rcl is asserted high to indicate that the lower nibble of the r bus (r3C0) is a network control character. when rcl is low, this nibble contains data. rcl is synchro- nous to bclk. this pin has internal pull-up. r7C0 receive bus (ttl input) the r bus is used to receive information from the external physical layer (phy) device. bytes clocked from the physical layer (phy) into the supernet 3 r-bus input are synchronous to the bclk. these pins have internal pull-up. rpar receive parity (ttl input) rpar is an input signal used to enhance error detection on the external phy interface r7:0 bus. rpar is an input signal used to implement even parity checking on r bus. if there is an odd number of 1s on {r7:0, rcu, rcl}, then rpar should be 1 and if there is an even number of 1s on {r7:0, rcu, rcl} then rpar should be 0. this pin has internal pull-up. rxafu3C0 receive bus tap for external af (ttl output, high impedance) the internal mac receive bus lines upper nibble are tapped and brought out as the rxafu 3C0 pins. these pins are used by an external af to do external sa and/or da match. rxafl3C0 receive bus tap for external af (ttl output, ttl input, high impedance) the internal mac receive bus lines lower nibble are tapped and brought out as the rxafl 3C0 pins. these pins are used by an external af to do external sa and/or da match. note: the rxafl[3:0] input pins are for diagnostic purposes only. rxafcu control upper for af receive bus (ttl output, high impedance) the rxafcu output signal is used to flag control symbols being presented on the nibble (3:0) of the rxafu bus. this signal is synchronous to bclk. if rxafcu is asserted high, the nibble on the rxafu bus is interpreted as a network control character. otherwise, it is interpreted as a data nibble. rxafcl control lower for af receive bus (ttl output, ttl input, high impedance) the rxafcl output signal is used to flag control symbols being presented on the nibble (3:0) of the rxafl bus. this signal is synchronous to bclk. if rxafcl is asserted high, the nibble on the rxafl bus is interpreted as a network control character. otherwise, it is interpreted as a data nibble. note: the rxafcl input is for diagnostic purposes only. x7C0 transmit bus (ttl output, high impedance) this eight-bit output bus is used to send control and data information to the external physical layer (phy) device to be transmitted over the medium. information on the x-bus output is synchronous to the bclk. xpar transmit parity (ttl output, high impedance) xpar is an output signal used to enhance error detection on the macexternal phy interface x7:0 bus. if there is an odd number of 1s on {x7:0, xcu, xcl}, then xpar should be 1 and if there is an even number of 1s on {x7:0, xcu, xcl} then xpar should be 0. xcu transmit control upper (ttl output, high impedance) the xcu output signal is used to flag control symbols being presented on the upper nibble of the transmit bus. this signal is synchronous to bclk. if xcu is asserted
amd p r e l i m i n a r y 12 supernet 3 high, the upper nibble of the x-bus is interpreted as a network control character. otherwise, it is interpreted as a data nibble. xcl transmit control lower (ttl output, high impedance) the xcl output signal is used to flag control symbols being presented on the lower nibble of the transmit bus. this signal is synchronous to bclk. if xcl is asserted high, the lower nibble of the x-bus is interpreted as a network control character. otherwise, it is interpreted as a data nibble. fotoff fiber optic transmitter off (ttl output, active low, high impedance) the fotoff signal, when asserted, causes the optical transmitter to turn off. sdi+, sdi- signal detect (pecl differential line receiver inputs) the sdi input signal pair is from the optical or copper transceivers to indicate whether the received optical or electrical signal is above its threshold. the inverted value of this signal is held in the phy_status_a register, and the lsdo interrupt bit in the phy is set whenever sdi becomes asserted. scrm scrambler/descrambler enable (dc input, active high) when this pin is strapped high, the supernet 3 is set to operate with a copper pmd and the scrambler/ descrambler is enabled. when the pin is strapped to ground, then the scrambler/descrambler function is disabled in the supernet 3, and the supernet 3 is set to operate with a fiber pmd. this pin is ored with the bit 0 (cipher_enable) in the plc_cntrl_c register and the result is indicated in the same bit (bit 0). the pmd selection and scrambler/descrambler (s/d) enabling is as follows: cipher_ scrm enable pin bit result low reset fiber pmd. s/d disabled. low set copper pmd. s/d enabled. high reset copper pmd. s/d enabled. high set copper pmd. s/d enabled. lsr 2C0 line state register (ttl output, high impedance) the lsr2C0 signals directly output the line_st field of the plc_status_a register to ring test and monitor equipment. ebferr elasticity buffer error (ttl output, active high, high impedance) ebferr indicates when an overflow or underflow condition occurs in the elasticity buffer. encoff encoder off (ttl input, active high) encoff signal turns off the 4b/5b encoding and decoding function of the plc core. ulsb unknown line state (ttl output, high impedance) the ulsb signal directly outputs the unkn_line_st bit of the plc_status_a register to ring test and monitor equipment. clock pins (3 pins) lsclk local symbol clock pin (ttl input) the lsclk is a 25 mhz clock. it is used by the plc core. bclk byte clock pin (ttl input) the bclk is a 12.5 mhz clock. it is used by the plc and the mac cores. bmclk buffer memory clock pin (ttl input) the bmclk is the clock signal that the mac core uses for generating the signals to the buffer memory. bmclk is driven with either a 12.5 or 25 mhz clock signal. if 12.5 mhz operation is desired, then this pin can be tied to bclk pin. if 25 mhz operation is desired, then this pin can be tied to lsclk pin. node processor (np) interface (35 pins) the following paragraphs describe the pins used to interface the supernet 3 with the node processor (np) or other control devices. the np interface is used for initializing the supernet 3 as well as for reporting status. csi chip select input (ttl input, active low) C asynchronous when npmode = 0 C synchronous when npmode = 1 the chip select input (active low) enables read and write operations to the supernet 3. in the asynchro- nous mode, the data output is enabled while csi and ds are both low and r/ w is high. in the synchronous mode, the data output is enabled while csi is low and r/ w is high.
p r e l i m i n a r y amd 13 supernet 3 ds data strobe/ (ttl input, active low) C asynchronous when npmode = 0 C synchronous when npmode = 1 the ds input (active low) is used in the handshake between the np and supernet 3 when the supernet 3 acts as bus slave during register accesses. in the asynchronous mode, this input signal is set by the node processor to transfer data between the np and the supernet 3. the direction of the data transfer is dictated by the logic level of the r/ w line. the np sets ds low to initiate a data transfer. ds is not used in the synchronous mode. the chip-select input ( csi ) must be low while ds is low in order to start an np bus transaction. npaddr7C0 np address bus (ttl input) the npaddr7C0 input lines allow direct access to supernet 3 internal registers. in addition, these lines are used to place supernet 3 into different operating states. the npaddr bus of the supernet 3 performs two control functions. first, the input on npaddr7C0 acts as an address, selecting the proper internal register for a read or write operation that is controlled by the r/ w pin. the data is either read onto or loaded from the 16-bit np bus. for a discussion of the results of read and load instructions, see the section under programming the formac plus in the supernet 2 data book. second, instructions or commands can be issued to supernet 3 by using the npaddr bus. npdata15C0 np data bus (ttl input, ttl output, high impedance) the np data bus is a 16-bit wide bidirectional data bus used to interface the supernet 3 to the node processor. data transfer on the np data bus can be synchronous or asynchronous depending upon the setting of the npmode pin. for asynchronous opera- tion, a two-wire handshake is provided through the ready and data-strobe ( ds ) lines. npmode np bus mode (ttl input) the level on the npmode pin defines the type of np-bus interface with the supernet 3. when npmode is strapped high, the np interface operates synchronously with bclk. when npmode is strapped low, asynchronous interface operation is selected. ready ready (ttl output, open drain, active low, high impedance) in asynchronous mode, the ready output (active low) is used in the handshake between the np and supernet 3. the supernet 3 ready output provides an asynchronous acknowledgment to the np that data transfer is complete. the supernet 3 asserts ready when it has put the data onto the np bus during a read cycle, or when it has taken the data from the np bus during a write cycle. ready is a response to the csi and ds inputs, and returns high after the csi or ds signals go high. in the synchronous mode, the ready line goes active on the bclk edge when csi and ds are active. ready goes inactive on the following bclk edge. in the case of loading/reading of the mdr (memory data register), ready goes active on the bclk edge after the completion of any pending data transfer from/to buffer memory. r/ w read/write select (ttl input) the r/ w line is used to select the type of access (i.e., read or write) between the supernet 3 and the np. if r/ w is high, data is read from the supernet 3 to the np. if r/ w is low, the data flow is from the np to the supernet 3. mintr1 maskable interrupt 1 (ttl output, open drain, high impedance) the mintr1 output (active low) is an attention line to the np. mintr1 , when active, indicates an interrupt due to one or more unmasked flags in status register 1. in general, the active state of mintr1 indicates that an unmasked interrupt condition or a transmit condition has occurred. mintr1 is deactivated once either the lower or upper 16 bits of status register 1 (st1l or st1u) are read. once mintr1 is asserted, all 32 bits of status register 1 must be read to enable any future interrupt on this pin. mintr2 maskable interrupt 2 (ttl output, open drain, high impedance) the mintr2 output (active low) is an attention line to the np. mintr2 , when active, indicates an interrupt due to one or more unmasked flags in status register 2. in general, the active state of mintr2 indicates that an unmasked interrupt condition, a receive condition, or a
amd p r e l i m i n a r y 14 supernet 3 change in ring status has occurred. mintr2 is deacti- vated once either the lower or upper 16 bits of status register 2 (st2l or st2u) are read. once mintr2 is asserted, all 32 bits of status register 2 must be read in order to enable any future interrupt on this pin. mintr3 maskable interrupt 3 (ttl output, open drain, high impedance) the mintr3 output (active low) is an attention line to the np. mintr3 , when active, indicates an interrupt due to one or more unmasked flags in status register 3. in general, the active state of mintr3 indicates that an unmasked interrupt condition, a receive condition in the second receive queue has occurred. mintr3 is deacti- vated once either the lower or upper 16 bits of status register 3 (st3l or st3u) are read. once mintr3 is asserted, all 32 bits of status register 3 must be read in order to enable any future interrupt on this pin. mintr4 maskable interrupt 4 (ttl output, open drain, high impedance) the mintr4 output (active low) is an attention line to the np. mintr4 , when active, indicates an interrupt due to one or more unmasked flags in the phy interrupt event (intr_event) register. in general, the active state of mintr4 indicates that a change in pcm state machine or timer expiration or counter overflow has occurred. mintr4 remains active until cleared by reading the intr_event register. when the mensnglint (mdreg 3, bit 10) is set, the supernet 3 generates only one interrupt ( mintr4 ) and the other interrupt lines ( mintr1 , mintr2 , and mintr3 ) are not toggled. the supernet 3 operates in a vectored interrupt mode, i.e., a vector register is read to determine which status register is the source of the interrupt. npmemrq node processor memory request (ttl input) the input signal npmemrq is a request by the node processor to obtain control of buffer memory. npmemack node processor memory access acknowledge (ttl output, high impedance) this signal indicates that an npmemrq has been granted and that the np now has control of buffer memory (addr-bus, rd, wr, cso , bdp, bd, and bdtag). if npmemack is forced low while npmemrq is active (due to a higher priority request), the np must release control of the bus within two bmclk periods after the npmemack line goes inactive. supernet 3/buffer memory interface (56 pins) addr15C0 buffer memory address (ttl output, high impedance) the 16-bit addr-bus provides the addresses that access the buffer memory. the address selection depends on the result of bus arbitration in the supernet 3. each memory access lasts for two bmclk clock cycles and the address is valid for both of these cycles. when buffer memory control has been released to the np, the addr bus is in the high-imped- ance state. note: as long as the use of the buffer memory has not been granted to the node processor or host (hsack and npmemack not active), the supernet 3 may drive the address lines even though no control signals are active. bd31C0 buffer memory data bus (ttl input, output, high impedance) the 32-bit bd bus interfaces the supernet 3 to the buffer memory or any external logic using this bus. these lines transfer data to and from the buffer memory for the supernet 3. these signals are synchronous to bmclk. bdp3C0 buffer data parity bus (ttl input, output, high impedance) the bdp3C0 bus contains the four byte-parity lines for the bd bus as shown in the following table: corresponding bd-bus lines parity lines bd7C0 and tag bit bdp0 bd15C8 bdp1 bd23C16 bdp2 bd31C24 bdp3 note: bd bus parity can be either even or odd, based on the state of the parity bit (bit 12) in mode register 2 (mdreg2). bdtag buffer data tag indication (ttl input, output, high impedance) in receive mode, this bit defines whether the information on the bd bus is data (bdtag = 0) or frame status (bdtag = 1). in transmit mode, when bdtag = 1, it indicates that the end of a frame has been reached, as indicated by the presence of a tag bit in both the last long
p r e l i m i n a r y amd 15 supernet 3 word and the descriptor word at the end of the frame. in transmit mode, when bdtag = 0, it indicates that the information on the bd bus is data, i.e., end-of-frame not yet reached. cso chip-select output (ttl output, high impedance, active low) the chip-select output (active low) is a select signal for buffer memory read and write operations. this line is in the high-impedance state when buffer memory control is released to the np. rd buffer memory read (ttl output, high impedance, active low) this output signal (active low) controls the buffer memory during a buffer-memory read accesses. this line is in the high-impedance state when buffer memory control is released to the np. wr buffer memory write (ttl output, high impedance, active low) this (active low) output signal, in its active-low state, allows write accesses to buffer memory. this line is in the high-impedance state when buffer memory control is released to the np. host/buffer memory interface (10 pins) all these signals are synchronous to bmclk. hsack host acknowledge (ttl output, high impedance) this signal indicates that the current host read/write request is being granted by supernet 3 and allows read/write accesses of buffer memory by the host. hsreq2C0 host request bus (ttl input) the host request bus specifies to supernet 3 the type of buffer memory access the host requires, as described in the following table. special-frame write requests are used to set up claim, beacon, and auto-void frames in the buffer memory (see the discussion under buffer memory operation in supernet 2 data book). these requests make use of the wpxsf register to set up special frames in the special-frame area. read request is used to retrieve received frames from buffer memory and store them in the system memory. write requests are used to set up frames in buffer memory for transmission. hsreq2 hsreq1 hsreq0 type of request 0 0 0 none. 0 0 1 read request: second receive queue* 0 1 0 special frame write request. 0 1 1 read request: receive queue. 1 0 0 write request: synchronous queue. 1 0 1 write request: asynchronous queue 0. 1 1 0 write request: asynchronous queue 1. 1 1 1 write request asynchronous queue 1. note: * only if two receive queue operation is selected through mdreg3. qctrl2C0 buffer queue control (ttl output, high impedance) the qctrl2C0 status output lines are encoded as de- scribed in the following table.
amd p r e l i m i n a r y 16 supernet 3 qctrl2 qctrl1 qctrl0 indicated status 0 0 0 (1) quiescent. (2) space remains for more data while loading a transmit queue 0 0 1 unloading transmit frame from synchro- nous queue 0 1 0 unloading transmit frame from asynchro- nous queue 0 0 1 1 unloading transmit frame from asynchro- nous queue 1 1 0 0 reserved 1 0 1 current transmit frame underrun 1 1 0 current transmit queue full. 1 1 1 current transmit queue almost full these signals communicate to the host the current condition of the transmit queues. this provides useful information for doing the host interface. the meaning of these states are as follows: a. qctrl[2:0] = 000 the quiescent state exists when supernet 3 is neither transmitting nor receiving. this state is also true while loading a transmit queue (making a write request to a queue) and not yet unloading it, and when there is space in the queue for more data. b. qctrl[2:0] = 001, 010 or 011 these states indicate unloading frame from the syn- chronous queue, asynchronous queue 0 or asynchro- nous queue 1, respectively. they are valid as long as the corresponding queue is not yet in the almost full or full state and, at the same time, the supernet 3 is reading out of the queue. the host can transfer more data into the corresponding queue when any of these states is present. these three combinations may appear one bmclk period later than the time indicated in the timing diagram. c. qctrl[2:0] = 101 this state is present when all of the following three conditions are satisfied: 1. the host has issued a write request for this queue 2. transmit fifo underrun occurs 3. transmit buffer-memory underrun occurs for this queue d. qctrl[2:0] = 110 when the transmit queue being requested is full, this state is presented at the queue control signals. note that this state does not exist in supernet 2, it is added in supernet 3. e. qctrl[2:0] = 111 this state means the number of free long words remaining in the transmit queue which the current write request is for has decreased to the almost-full value (afull3-0) programmed in mode register 2. this signal condition is asserted for one bmclk cycle only as in the formac plus if the menafull bit in the mode register 3 is not set. if this bit is set, this state will remain for every cycle as long as the queue is in almost full condition and it is not yet full. note: if afull3-0 is set to 000, this state is not pre- sented, even when the transmit fifo in buffer memory is full. rdata1 receive data for receive queue #1 (ttl output, high impedance) this signal indicates that received data is present in the buffer memory and is ready to be transferred by the host to system memory. read requests are not acknowl- edged when rdata1 is inactive. rdata2 receive data for receive queue #2 (ttl output, high impedance) this signal indicates that received data is present in the buffer memory and is ready to be transferred by the host to system memory. read requests are not acknowl- edged when rdata2 is inactive. special functions and control pins (16 pins) flxi flush/inhibit (ttl input) the supernet 3 flxi pin can be programmed to perform either of two functions: it can provide a flush received frame function for the chip or it can provide an unconditional transmit-inhibit function. if the flush function is selected and the pin is asserted by external logic, then the incoming frame is flushed. the buffer memory pointers are not advanced from where they were before the frame was received. this prevents unwanted frames and fragments from occupy- ing receive buffer space and taking up the buffer memory bus bandwidth. if the transmit inhibit function is selected and the pin is asserted by external logic, then the supernet 3 completes transmitting the current frame (if transmit- ting) releases the token and no further transmissions can occur until the pin is deasserted. during the time that the transmit inhibit function is enabled, the network timers and state machines operate normally.
p r e l i m i n a r y amd 17 supernet 3 rs5C0 receive status (ttl output, high impedance) the receive-status (rs4C0) pins indicate the type of frame received, and the condition of the receive state machine. the rs4C0 status output pins are encoded as illustrated in table 3 in the supernet 2 data book and the enhancements rs5C0 are described here. rs5 rs4 rs3 rs2 rs1 rs0 indicated status 0xxxx xas in supernet 2 formac plus 10000 0 reserved 1 0 x 0 0 1 starting delimiter and non-data symbol received 10001 0 osm mode: stripping frame 10001 1 reserved 10010 0 reserved 10010 1 frame abort 10011 0 frame flush 10011 1 reserved through 11111 1 reserved xs3C0 transmit status (ttl output, high impedance) the transmit-status (xs3C0) pins indicate the transmit status conditions of the mac and are valid for one clock cycle. these status signals are not present for repeated or stripped frames. these status output pins are en- coded as illustrated in table 4 (supernet 2 data book) and the enhancements are described here. xs3 xs2 xs1 xs0 indicated status 0000 quiescent. 0001 transmit aborted. 0010 token issued 0011 reserved. 0100 transmitting syn- chronous queue. 0101 transmitting asyn- chronous queue 0. 0110 transmitting asyn- chronous queue 1. 0111 reserved 1000 reserved 1001 initiated claim. 1010 initiated beacon. 1011 initiated void 1100 mac frame aborted 1101 void frame aborted xdamat external destination address match (ttl input, active low) this input provides a means for additional destination- address detection external to the supernet 3. this pin should be tied high when external destination-ad- dress detection is not used. this input should remain asserted for at least one bclk cycle, and must be deasserted for at least one bclk cycle before a subsequent external destination address match is recognized. the xdamat pin which is generated by the external af is logically ored with the af_da output signal gener- ated by the internal af logic. this pin should be tied high when external address detection (such as an external af) is not used. xda_xact external destination address exact match (ttl input, active low) this input indicates whether the external address match was exact (low) or inexact (high). this input should remain asserted for at least one bclk cycle, and must be deasserted for at least one bclk cycle before a subsequent external source address match is recog- nized. it must be asserted and deasserted in an identical
amd p r e l i m i n a r y 18 supernet 3 fashion to the xdamat pin. this input is used in conjunction with the xdamat pin as follows: match action xda_xact and xdamat a, c indicators set and frame copied*. xda_xact and xdamat invalid combination. ignored by mac. xda_xact and xdamat a, c indicators not set and frame copied. xda_xact and xdamat no action. * frame is copied if valid frame or if in promiscuous or limited promiscuous mode. in osm, the a, c indicators are set according to the osm rules if bits 4, 5 (meind0,1) are set. the xda_xact pin which is generated by the external af is logically ored with the af_dax output signal generated by the internal af logic. this pin is enabled only if the menxact bit in the mode register 3 is set. this pin should be tied high when external address detection (such as an external af) is not used. xsamat external source address match (ttl input, active low) this input provides a means for additional source-ad- dress detection external to the supernet 3. this pin should be tied high when external source-address de- tection is not used. this input should remain asserted for at least one bclk cycle, and must be deasserted for at least one bclk cycle before a subsequent external des- tination address match is recognized. the xsamat pin which is generated by the external af is logically ored with the af_sa output signal gener- ated by the internal af logic. this pin should be tied high when external address detection (such as an external af) is not used. xsa_xact external source address exact match (ttl input, active low) this input indicates whether the external source ad- dress match was exact (low) or inexact (high). this input should remain asserted for at least one bclk cycle, and must be deasserted for at least one bclk cycle before a subsequent external source address match is recog- nized. it must be asserted and deasserted in an identical fashion to the xsamat pin. this input is used in con- junction with the xsamat pin as follows: match action xsa_xact and xsamat frame stripped. xsa_xact and xsamat invalid combination. ignored by mac. xsa_xact and xsamat frame not stripped. xsa_xact and xsamat no action. the xsa_xact pin which is generated by the external af is logically ored with the af_sax output signal generated by the internal af logic. this pin is enabled only if the menxact bit in the mode register 3 is set. this pin should be tied high when external address detection (such as an external af) is not used. rst reset (ttl input) the rst signal (active low) is an asynchronous input that initializes the internal supernet 3 state machines and registers. once rst is asserted low, it must remain asserted for at least twenty bclk cycles. when it is deasserted the supernet 3 is ready to begin normal operation only after 750 lsclk cycles. the 750 lsclk cycles are needed for calibration of the pdx core. assertion and deassertion are asynchronous. a warm reset (assertion of rst after the device is in operation) will cause device outputs to be unpredictable until the device is initialized. testability interface (5 pins) tck test clock in (ttl input) tck provides the clock for the test logic. any stored- state devices contained in the test logic must retain their state indefinitely if the signal applied to tck is held high or low. tms test mode select in (ttl input, synchronous to tck) the test mode select input directs the operation of the generation of the tap controller. the state of the tms signal is sampled on the rising edge of tck. if for some reason tms is not driven externally, the tap controller should behave as if this signal were driven with a logic 1 (internal pull-up). tdi test data in (ttl input, synchronous to tck) this pin provides for the application of serial instructions and data. the state of this signal is sampled on the rising edge of tck. if for some reason tdi is not driven externally, the test logic should behave as if a logic 1 were applied to this signal (internal pull-up). tdo test data output (ttl output, 3-state, synchronous to tck) this pin provides the serial output for instructions and data from the test logic. no inversion of data is allowed between tdi and tdo during shift operations. the state of tdo changes on the falling edge of tck. tdo is in the high impedance state except during shifting operations.
p r e l i m i n a r y amd 19 supernet 3 trst test reset (asynchronous ttl input, active low) this input is provided for asynchronous initialization of the tap controller. when a logic 0 is applied, the tap controller must go to the test-logic-reset state. if for some reason trst is not driven externally, the test logic should behave as if a logic 1 were applied (internal pull-up). this pin can not be used to initialize any system logic. power and ground (37 pins) gnd ground (input) there are 23 ground (gnd) pins on the supernet 3 chip. they must all be connected to a common external ground reference. v cc +5 v power (input) there are 15 pins carrying +5-v power (vcc) on the supernet 3 chip. they must all be connected to a 5 v 5% source. supernet 2 features not supported the following features are not supported in supernet 3 in any mode. n supernet 3 supports the tag mode of operation for the system-to-buffer-memory and network (mac)-to-buffer-memory interfaces. non-tag mode of operation is no longer supported. n supernet 3 supports three transmit queues: synchronous, async0 and async1. async2 is no longer supported. n the disable carry (discry) function is no longer supported. setting of the discry bit in the mode register 1 (mdreg1: bit 6) allowed segmenting of the trt, tht, tvx, and tmsync registers into 4 and 5 bits each for diagnostic purposes. this is no longer necessary due to the testability enhancements. n single-frame receive mode is no longer supported. n symbol control is no longer supported in the mac. this function was used for diagnostics purposes to transmit user-controlled data, control and violation symbols to the phy. n the hold function and associated logic is eliminated and it is no longer supported. miscellaneous changes from supernet 2 n the current queue almost full (afull) encoding of the qctrl signals is modified to be asserted for every clock after the afull boundary is crossed until the queue is full while a host write request is asserted. currently, the signal is asserted for one clock only. n xda_xact' and xsa_xact' input signals are provided for the external cam (if implemented). n for increased robustness, all internal tri-state busses will have a driven default state and will not be allowed to float. n the node processor access interface has been streamlined to two modes: 1) the formac plus asynchronous access mechanism for accessing all blocks. 2) the plc two-cycle synchronous access mechanism for accessing all blocks. n there are four interrupt pins: two generated by the two mac status registers, one generated by the af and one generated by the phy status register. explanation of enhancements status pins xs 3:0 transmit status pins (outputs) an additional transmit status pin has been added to provide more transmit information. the encoding of the status pins is fully backward compatible with the supernet 2 chipset. the enhanced encoding is enabled by setting the menxs bit in the mode register 3 (mdreg3). the encoding of the xs pins is as follows: xs3 xs2 xs1 xs0 indicated status 0000 quiescent 0001 transmit aborted 0010 token issued 0011 reserved 0100 transmitting syn- chronous queue 0101 transmitting asyn- chronous queue 0 0110 transmitting asyn- chronous queue 1 0111 reserved 1000 reserved 1001 initiated claim 1010 initiated beacon 1011 initiated void 1100 mac frame aborted 1101 void frame aborted 1110 reserved 1111 reserved
amd p r e l i m i n a r y 20 supernet 3 rs 5:0 receive status pins (outputs) an additional receive status pin has been added to provide more receive information. the encoding of the status pins is fully backward compatible with the supernet 2 chipset. the enhanced encoding is enabled by setting the menrs bit in the mode register 3 (mdreg3). the encoding of the rs pins is shown on the following table. rs5 rs4 rs3 rs2 rs1 rs0 indicated status 0xxxx xas in supernet 2 formac plus 10000 0 reserved 1 0 x 0 0 1 starting delimiter and non-data symbol received 10001 0 osm mode: stripping frame 10001 1 reserved 10010 0 reserved 10010 1 frame abort 10011 0 frame flush 10011 1 reserved through 11111 1 reserved qctrl 2:0 queue control pins (outputs) the encoding of the qctrl pins is as follows: qctrl2 qctrl1 qctrl0 indicated status 0 0 0 (1) quiescent. (2) space remains for more data while loading a transmit queue 0 0 1 unloading transmit frame from synchronous queue 0 1 0 unloading transmit frame from asynchronous queue 0 0 1 1 unloading transmit frame from asynchronous queue 1 1 0 0 reserved 1 0 1 current transmit frame underrun 1 1 0 current transmit queue full 1 1 1 current transmit queue almost full slower buffer memory interface the buffer memory interface has been modified ena- bling slower srams (35 ns) to be used as buffer memory. this reduces the system cost. the interface is fully backward compatible with the supernet 2 buffer memory interface. clocking lsclk local symbol clock pin (input) the lsclk is a 25 mhz clock. it is used by the plc-s and pdx cores. bclk byte clock pin (input) the bclk is a 12.5 mhz clock. it is used by the plc-s and the mac cores. bmclk buffer memory clock pin (input) the bmclk is the clock signal that the mac core uses for generating the signals to the buffer memory. bmclk is driven with either a 12.5 or 25 mhz clock signal. if 12.5 mhz operation is desired, then this pin must be tied to bclk pin. if 25 mhz operation is desired, then this pin must be tied to lsclk pin. a, c indicators the setting of the a, c indicators has been modified to allow the indicator setting to be selectable in any of the modes: online, online special mode, or external loop- back. the a, c indicators can be set as normal, msc method, or not modified at all. the modified setting of the a, c indicators can be selected by setting the
p r e l i m i n a r y amd 21 supernet 3 meind0 and meind1 bits in the mode register 3 (mdreg3). meind1 meind0 description 0 0 default supernet 2 behavior 0 1 set a, c as in online mode. this overrides osm status indicator setting (i.e., if mdreg1 bits mmode2=0, mmode1=1, mmode0=0). 1 0 set a, c as in osm mode. this overrides the mmode2C0 bits in the mdreg2 for the status indicator setting. 1 1 do not set the a, c indicators in any mode.
amd p r e l i m i n a r y 22 supernet 3 meind[1:0] osm en_xact xda_xact xda da_int a_flag c_flag a_bit c_bit 00 0 x x 0 0 0 0 nm nm 00 0 x x x 1 1 111 00 0 x x 1 0 1 111 00 1 x x 0 0 0 0 nm nm 00 1 x x x 1 1 111 00 1 x x 1 0 0 1 nm 1 01 x 0 x 0 0 0 0 nm nm 01 x 0 x x 1 1 111 01 x 0 x 1 0 1 111 01 x 1 x 0 0 0 0 nm nm 01 x 1 x x 1 1 111 01 x 1 0 1 0 0 1 nm 1 01 x 1 1 1 0 1 111 10 x 0 x 0 0 0 0 nm nm 10 x 0 x x 1 1 111 10 x 0 x 1 0 0 1 nm 1 10 x 1 x 0 0 0 0 nm nm 10 x 1 x x 1 1 111 10 x 1 0 1 0 0 1 nm 1 10 x 1 1 1 0 1 111 11 x x x x x 0 0 nm nm where, meind[1:0] bit 4 and 5 of mdreg3 osm - bit 14-12 of mdreg1 en_xact - bit 2 of mdreg3 xda_xact - pin 113, is an active low signal. 1 indicates signal is active and 0 indicates signal is inactive xda - pin 114, is an active low signal. 1 indicates signal is active and 0 indicates signal is inactive. da_int - internal da match signal a_flag - da match flag c_flag - frame copied flag a_bit - a bit in the end delimiter c_bit - c bit in the end delimiter x - dont care condition. nm - not modified by the mac
p r e l i m i n a r y amd 23 supernet 3 transmit queues async2 transmit queue not supported the supernet 3 supports synchronous, and two asynchronous priorities. the async2 queue is no longer supported. this causes the following changes: 1. tpri2 (16-bit priority register for asynchronous queue 2) is no longer implemented. 2. eaa2, wpxa2, swpxa2, rpxa2 registers are no longer implemented. 3. the clear asynchronous queue 2 lock and transmit asynchronous queue 2 commands are no longer available in the command registers 1 and 2, respectively. the value 0x18 in command register 1 and 0x08 in command register 2 shall not be decoded to any other instruction. these values are reserved. 4. the stefrma2, stecfrma2 and stxabra2 bits in the upper 16 bits of the status register 1 (st1u) are reserved and set to zero. similarly sqlck2, stxinfla2, spcepda2, and stbura2 are reserved and set to zero. 5. the qctrl[2:0] = 100 encoding is now invalid. this encoding indicated request transfer into asynchronous queue 2 which is no longer available. the encoding is reserved and shall not be used to indicate any other qctrl condition. (see note) 6. the hsreq[2:0] = 111 is now decoded as write request: asynchronous queue 1. in formac+ this request indicated a write request to asynchronous queue 2 which is no longer available. note: if the encoding hsreq[2:0] = 111 is used, the supernet 3 would not use the qctrl[2:0] = 100 encoding to indicate status of asynchronous queue, but instead the qctrl[2:0] = 011 (request transfer into asynchronous queue 1) encoding would be indicated by supernet 3 and external logic could be added to invert this encoding to be compatible with formac+. afull encoding of qctrl signals modified the qctrl2C0 pins provide the encoded status of the buffer memory transmit queues. the value qctrl[2:0] = 111, current queue almost full, was asserted for one host write cycle in supernet 2. this signal shall now be generated for every host write cycle until the queue becomes full or the almost full threshold is no longer exceeded. this new signal assertion is implemented only if the bit menafull is set in mode register 3 (mdreg3) transmit frame format in supernet 2 transmit frames must consist of aligned data, i.e. all words in the buffer memory must contain four valid bytes, except that the last data word may consist of less than four bytes. this required that the frame control (fc) of the frame be written as the most significant byte of the frame data long word. supernet 3 would support an enhanced feature, where in the frame control (fc) could be any byte of the frame data long word. the destination address (da) would follow the fc as the next byte in any mode of operation. this feature is enabled only when the bits menfcloc (bit 12 & 13) is set in mode register 3 (mdreg3). upon reset these bits would be both zero and the frame control (fc) has to be written as the most significant byte of the frame data long word. the following table describes the decoding of the menfcloc bits in the mode register 3 (mdreg 3): if menfcloc 13-12 = 00 01 10 11 case 1: lsb = 0 then fc starts at: byte 1 byte 2 byte 3 byte 4 (mdreg 2 bit 11) (msbyte) (lsbyte) case 1: lsb = 1 then fc starts at: byte 4 byte 3 byte 2 byte 1 (mdreg 2 bit 11) (msbyte) (lsbyte)
amd p r e l i m i n a r y 24 supernet 3 non-tag mode of operation no longer supported the supernet 3 only supports the tag mode of operation for transmit and receive. the non-tag mode of operation is no longer supported. all functionality related to the non-tag mode of operation is removed. this causes the following changes: 1. bits [7:4] in status register 1 upper (st1u), indicating transmit end of chain of frames (stecfrm-s, a0, a1, a2) are now reserved. they shall be read as zero. 2. bits [7:4] in status register 1 lower (st1l), indicating transmit instruction full (stxinfl-s, a0, a1, a2) are now reserved. they shall be read as zero. 3. in command register 2, the commands transmit synchronous queue [0x01], transmit asynchronous queue 0 [0x02], and transmit asynchronous queue 2 [0x08] are now reserved. these values shall not be decoded to any other instruction. 4. bit 15 in mode register 2 (mdreg2) indicating buffer memory mode is now decoded differently. this bit shall be read as one upon reset, indicating tag mode of operation. if programmed to zero, the modified tag mode of operation will be enabled. this bit selection applies to both receive queues if mendrcv bit is set in mode register 3 (mdreg 3). modified tag mode operation the supernet 3 will have two modes of host interface to buffer memory. the two modes are distinct and independent ways of accessing the buffer memory depending upon the selection of the tag mode or modified tag mode. in tag mode the supernet 3 provides the local buffer management, i.e the queue pointers are maintained by supernet 3. modified tag mode is used when the non-tag mode users of formac+ are redesigning for supernet 3. loading of transmit frames in modified tag is identical to tag mode. the unloading of received frames is different in modified tag mode of operation. the format of a receive frame is as shown figure 1. the first long word in each frame consists of a 16-bit status word and a 16-bit word that gives the length of the frame in bytes. the status/length word is followed by the data words. the location of the first byte in the first long word of data is defined by the byte boundary bits rxfbb1C0 of mode register (mdreg 2). at the end of the frames that make up a receive queue, supernet 3 writes a long word with all bits as a logic 0, which indicates that there is no more data in this queue. the only function of this word is to act as an end delimiter. note that the msvalid bit in bit 31 of the status word at the start of the frame is always in the logic 1 state. also, when another frame follows this queue, it overwrites the end delimiter word with the receive status word of the new frame. after each frame has been written into buffer memory, supernet 3 write the status and frame length at the start of each frame, and places an end-indicator word of all 0s at the end of the queue. once a frame is completely received, the status bit srcomp in status register 2 (st2u) is set. if the received frame is aborted, the supernet 3 will write the status word indicating the aborted status (bit 30) and the length field bits will be all zero. if the receive queue has an overflow condition during frame reception, the status register bit indicating srcvovr in status register 2 (st2u bit 11), is set high and the frame is aborted. an overflow also sets the msrabt bit (bit 30) in the receive frame status word of the incomplete frame. the received frames are unloaded by the host from the buffer memory by using the host request pins (hsreq). the rdata signal is always in the 0 state and receive frame threshold (rthr) is not applicable in modified tag mode for asserting the rdata pin. if dual receive queue operation is selected (mendrcv, bit 11 in mdreg 3) then the receive status information would be indicated in the corresponding status register (st2u for recv1 and st3u for recv2).
p r e l i m i n a r y amd 25 supernet 3 0p3p2p1p0 15 16 31 frame 1 status word 1 frame 2 frame 1 length status word 2 frame 2 length status word 3 frame 3 length aborted frame status word 4 frame 4 length status word 5 frame 5 length frame 5 all zeros 19574a-2 aborted frame t 1 0 . . . . . . . . . . 0 0 . . . . . . . . . . 0 1 1 1 0 figure 1. memory receive queue (modified tag mode)
amd p r e l i m i n a r y 26 supernet 3 transmit command the supernet 3 provides a feature to control transmission of frames from async1 queue in both tag and modified tag modes. this feature can be enabled by programming the mentrcmd (bit 14) in mode register 3 (mdreg3). this feature, when en- abled, would wait for the transmit asynchronous queue1 command. this feature would be applicable only to async1 queue. the supernet 3 has to be in initialize mode to enable the transmit command feature. once this is enabled the supernet 3 will not transmit from async1 queue unless a command in given by the node processor. to disable this feature, the supernet 3 has to be in initialize or memory active mode. the read pointer (rpxa1), write pointer (wpxa1) and shadow write pointer (swpxa1) are under the control of the user. the frames to be transmitted could be loaded by the host into the buffer memory either by using the host request pins, or by using npdma pins or by using the marw and mdr registers. when using the host request pins, the supernet 3 responds to the host request as in any mode, except that the transmit threshold register value would be ignored. ifpc would not monitor the frames being loaded into buffer memory for memory full condition, buffer empty condition etc. after the last data word and descriptor are written to complete the frame, transmit command can be issued to start transmission. when npmemrq pin is used by the np the address bus and memory control signal lines are placed in the high-impedance state by the supernet 3. this gives the np free access to load the buffer memory, however, the frames must conform to the format defined. the np is also responsible in keeping track of async 1 pointers (wpxa1, rpxa1, ltdpa1) prior to issuing the transmit command. when the np uses the marw and mdr to load the buffer memory, it first loads the marw with the starting address of the frame. then the mdru is loaded from the np, followed by the mdrl. as soon as the second 16-bit data word is loaded, supernet 3 sets an internal request to move the contents of the mdr to the buffer memory. the marw is incremented after the write operation is completed. the np could use the set tag command in cmdreg2 to set the tag bit for the mdr write cycle, however, the tag bit command is valid for one np write operation only. after the complete frame(s) have been loaded for transmission, the np has to program the last transmit descriptor pointer (ltdpa1) to be equal to the address of the last descriptor written. also, the async1 queue (wpxa1) write pointer needs to be programmed to ltdpa1 + 1. the supernet 3 would assume that the read pointer is at the correct address. the np should then give an instruction to supernet 3 to transmit the async1 queue. the supernet 3 would transmit till the read pointer (rpxa1) equals the last transmit descriptor pointer (ltdpa1). the user could load multiple frames before issuing the command. the np cannot issue more than one transmit command until the supernet 3 indicates the end of transmit command status (stecmda1) in status register 1 - upper (st1u). tdat loopback the supernet 3 provides a feature to control the loopback of transmit datapath after the plc (tdat) back to the receive data path of the plc (rdat). this loopback path is enabled when mdreg3, bit 15 (mentdlpbk) bit is set to logic 1. mode register 3 (mdreg3) an additional 16-bit mode register 3 is provided. the new features and modifications are enabled by the setting of the bits in the mdreg3. by default, the register bits are reset to zero. this register can only be written when the supernet 3 is in initialize or memory active modes.
p r e l i m i n a r y amd 27 supernet 3 lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-3 menrs menxct menafull meind0 meind1 menqctrl menrqaunlck mendas menplccst mensglint mendrcv menfcloc0 menfcloc1 mentrcmd mentdlpbk menxs figure 2. register 3 (mdreg3) (npaddr = 60h) menrs (bit 0) enable enhanced receive status encoding. menxs (bit 1) enable enhanced transmit status encoding. menxct (bit 2) enable exact/inexact matching. menafull (bit 3) enable enhanced qctrl encoding for afull. meind0, meind1 (bits 4, 5) enables enhanced a, c indicator setting. menqctrl (bit 6) enables enhanced qctrl encoding. menrqaunlck (bit 7) enable receive queue auto unlock. mendas (bit 8)* enables das connections by controlling the mux. menplccst (bit 9) enables counter segmentation test in plc block mensglint (bit 10) enables vectored interrupt reading. the mintr4 is used as the vectored interrupt. mendrcv (bit 11) enables dual receive queue operation. menfcloc (bit12,13) enables the fc location within the frame data long word. mentrcmd (bit 14) enables the async1 queue to transmit only after the command is issued. mentdlpbk (bit 15) enable tdat to rdat loopback * this bit should only be set if the external phy is available for a das configuration. bit description
amd p r e l i m i n a r y 28 supernet 3 address space the formac plus uses seven pins (0C6) and the plc uses five pins (0C4). the new address space uses eight pins (0C7) with the following decoding: address 7:0 comment 00C7f mac addresses. up to 128 addresses can be accessed. currently 127 addresses are used. full backward compatibility 80Caf phy addresses. currently the plc has 28 registers defined. this would allow up to 48 addresses to be accessed b0Ccf address filter (af) addresses. note that the af currently has ten addresses all of which are read /written by the user d0Cdf pdx address space. there are 16 possible addresses. e0Cff reserved for future use interrupts there are four interrupts: two for the mac, one for the mac/bist, and one for the phy. the two interrupts for the mac ensure that the interrupt service routine (isr) does not have to perform two reads to determine which of the status registers generated the interrupt. the third interrupt is generated when the bist operations are complete or when the second receive queue has changes in its status. the fourth interrupt indicates the status of the phy. interrupt mechanisms scalar: there are four interrupts, two from mac, one from mac and bist, and one from phy. these interrupts can be tied together externally or serviced separately. this method is the default and is backwards compatible with the supernet 2 interrupt generation and servicing mechanisms. vectored: only one interrupt is monitored (mintr4), and upon an interrupt being generated, a 16-bit maskable interrupt vector register (ivr) is read. each bit in the vector register indicates the source of the interrupt. the vector register bits are: bits interrupt source bit 0 mac status register 1 upper (st1u) bit 1 mac status register 1 lower (st1l) bit 2 mac status register 2 upper (st2u) bit 3 mac status register 2 lower (st2l) bit 4 mac status register 3 upper (st3u) bit 5 mac status register 3 lower (st3l) bit 6 phy interrupt event register (intr_event) bit 7C15 reserved. shall be read as zero. this method of interrupt generation and processing can be enabled by setting the mensglint (bit 10) in the mode register 3 (mdreg3). if enabled, this mechanism requires the user to read the interrupt vector register (ivr), locate the bit which is set, and read the corresponding interrupt event or status register. each bit in the ivr is maskable. the interrupts can be unmasked by setting the corresponding bit in the interrupt mask register (imr). by default, all bits in the imr are reset (to zero) and all interrupts are masked. the mask register bits are: bits interrupt source bit 0 mask mac status register 1 upper (st1u) interrupt. bit 1 mask mac status register 1 lower (st1l) interrupt. bit 2 mask mac status register 2 upper (st2u) interrupt. bit 3 mask mac status register 2 lower (st2l) interrupt. bit 4 mask mac status register 3 upper (st3u) interrupt bit 5 mask mac status register 3 lower (st3l) interrupt. bit 6 phy interrupt event register (intr_event) interrupt. bit 7C15 reserved. shall be read as zero. once mintr4 is activated, the corresponding status or event register must be read to enable any further interrupt on mintr4. receive flush/transmit inhibit pin flxi (input) the hoflxi pin is now the flxi pin and the hold function is no longer supported. the functional timing for this pin is as specified in the supernet 2 data book. if the flush function is selected and the pin is asserted by external logic, then the incoming frame is flushed. the buffer memory pointers are not advanced from where they were before the frame was received (i.e. wpr = swpr). the receive flush pin is asserted by the host to flush the current frame being received based on an external criterion regardless of the address match. this prevents unwanted frames and fragments from occupying receive buffer space and taking up the buffer memory bus bandwidth. if receive threshold is non-zero, then the frame will be flushed only if the pin is asserted before the threshold is crossed. refer to timing diagram for details. if the transmit inhibit function is selected and the pin is asserted by external logic, then the supernet 3 completes transmitting the current frame
p r e l i m i n a r y amd 29 supernet 3 (if transmitting), releases the token, and no further transmissions can occur until the pin is deasserted. during the time that the transmit inhibit function is enabled the network timers and state machines operate normally. as a result of the change to the flxi pin, which of the two functions is selected depends upon the state of flxi bits, as follows: flxi pin flxi1 flxi0 function implemented 0 0 0 normal operation 1 0 0 normal operation 0 0 1 normal operation 1 0 1 flush received frame 0 1 0 normal operation 1 1 0 inhibit transmission 0 1 1 reserved 1 1 1 reserved upon reset, the flxi1:0 bits would read all zeros. single frame receive mode the single frame receive mode function has been removed from the supernet 3. all associated status, modes and commands are deleted and replaced with reserved. this causes the following changes: 1. status register 2 upper: the receive frame (srcvfrm) bit 10 and receive frame counter overflow (srfrctov) bit 9 are now reserved and return a value of zero when read. 2. command register 2: the enable receive single frame command (0x40) is no longer a valid command. this is now reserved. 3. mode register 1: the single-frame receive mode bit [15] is no longer valid. it is now a reserved bit and shall return a value of zero when read. receive queue operation supernet 3 provides a new feature where the user can configure the buffer memory for incoming valid frame into two separate receive queues. the type of frames that each queue would receive is selected in a separate register, the frame selection register (frselreg). to enable two receive queues operation, mendrcv bit in mode register 3 (mdreg3) needs to be set. if this bit is cleared, which is the case at the time of reset, then supernet 3 behaves like f+ (i.e only one receive queue is supported, and supernet 3 defaults to receive queue 1). if mdreg3 bit 11, mendrcv and both recvx3:0 in frame selection register (frselreg) is programmed to be 0000 then the supernet 3 would behave like formac+ and the second queue is ignored. however, if one of the recvx3:0 bits in frselreg are programmed to be 0000 then the corresponding queue would receive all frames except the frame type selected for the other queue. only the second receive queue (i.e. recv2) can be programmed to be 0000. programming the recv1 bits in the frame selection register (frselreg) with 0000 and recv2 bits with a non-zero selection, will result in no data being written in the recv1 queue. only the frame type selected by recv2 bits will be received in the second queue.
amd p r e l i m i n a r y 30 supernet 3 lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-4 recv1(0) recv1(1) recv1(2) recv1(3) recv2(0) recv2(1) recv2(2) recv2(3) reserved enxmtadswap enrcvadswap reserved reserved reserved reserved reserved figure 3. frame selection register (frselreg) options for selecting frame types under two receive queues operation is as follows: recvx3:0 frame type 0000 receive all frames except the frame type selected for other queue. recv1[3:0] bits cannot be programmed as 0000 when recv2[3:0] bits are non-zero. 0001 llc (includes both sync. & async. llc frames) 0010 smt 0011 non-smt (includes all non-smt frames except mac & void, mac & void frames are received if promiscuous mode is selected in mdreg1) 0100 implementor 0101 mac 0110 sync. llc 0111 async. llc 1000 void 1001 async. llc & smt 1010C1111 reserved the above selection of frames for each queue is made by programming appropriate bits in the frame selection register (frselreg) and is applicable to only those frames that meet the criteria for copying as defined by addet2C0 bits of mode register 1 (mdreg1) of supernet 3. the following restrictions apply to frame selection: 1. the same selection is not allowed for both queues. programming the frame selection register with the same selection in both the recvx3:0 bits would result in supernet 3 operating as a single receive queue mode, and would default to receive queue 1. this overrides the mendrcv bit in the mode register 3 (mdreg3). 2. if high level selection option is used for a given frame type, then sub-level selection for the same frame type is not allowed [i.e. if llc (0001) option is selected for one queue, then sync. llc (0110) or async. llc (0111) or async. llc & smt options are not allowed for the second queue]. if a selection is made where one frame type is a sub-set of the other frame type, the selection made for recv1 queue supersedes the selection for recv2 queue.
p r e l i m i n a r y amd 31 supernet 3 the two receive queues will have independent receive fifos. there will be two instructions to clear locks on the two receive queues. clear receive queue lock (instruction code 20h) will be for recv1 and the new instruction clear receive2 queue lock (instruction code 21h) will be for recv2 queue. clear all queue locks command would clear locks on all queues. clearing the queues would enable further transfer of data received from the corresponding receive fifo. the received data present in the buffer memory for each queue is indicated by the corresponding rdata pin. recv1 data is indicated by rdata1 and recv2 data is indicated by rdata2. if the two receive queue feature is not selected, rdata1 would indicate received data present in buffer memory. read requests will not be acknowledged when rdata pins are inactive. the status bits srcomp, srbmt, srabt, srbfl, srcvovr of status register 2 upper st2u (bit 15C11) would be for recv1 queue. the status bits srcomp2, srbmt2, srabt2, srbfl2, srcvovr2 of status register 3 upper st3u (bit 15C11) would be for recv2 queue. the host interface to read the data received in the second receive queue would use hsreq2C0 lines and the encoding would be hsreq[2:0] =001. address bit swapping the supernet 3 provides the necessary logic for swapping the address fields within each frame between fddi and ieee canonical bit order. this involves a bit reversal within each byte of the address field. this feature is user selectable for transmit, receive or both, however, once selected the bit swapping applies to all queues. this is an useful feature for bridging ethernet to fddi or for other higher level protocols. bit 15 of the frselreg, enrcvadswap, enables the bit swap on the receive queues. the fc field of the received frame would decide whether the frame has long address or short address. bit 14 of frselreg, enxmtadswap, enables the bit swap of the transmit queues. the fc field of the frame to be transmitted will decide whether the frame to be transmitted has long address or short address. the crc written into the buffer memory will be the same as received. this logic will not re-generate crc after bit swapping on the receive queues. the user can set mdreg2 bit 14, strpfcs, to strip receive fcs and prevent fcs being copied into the buffer memory. on the transmit side, the address bits are swapped before the crc generator, and therefore, the transmitted crc will be correct for the bit swapped address. auto-unlocking of receive queues the buffer memory receive queue is locked out for any further input when the receive buffer is full (rprx = wprx after an increment of wprx). the lock can be cleared using the node processor commands clear receive queue lock (20h) or clear all queue locks (3fh). once the lock has been cleared, the receive buffer is available for further input. however, the node processor has to clear the lock by using the cmdreg1 to enable reception of frames in the receive buffer. the supernet 3 provides an enhancement feature to allow automatic unlocking of the receive queue based on user-programmable host read count threshold. to enable this feature, menrqaunlck bit in mode register 3 (mdreg3) needs to be set. if this bit is cleared, which is the case at the time of reset, the supernet 3 behaves like formac+ (i.e upon buffer full condition the receive queue is locked for further input and needs a node processor command to clear the lock). if menrqaunlck is enabled, the unlckdly register needs to be programmed with a 8 bit threshold value for each receive queue. upon receive buffer full condition, the unlckdly value times 4 will be loaded into a counter. the counter will count down for every corre- sponding host read receive acknowledge. after the number of host read receive acknowledges exceeds the user programmable count (unlckdly) times 4, the supernet 3 would start receiving frames into the corresponding receive buffer queue the srbflx bit in st2u and st3u would indicate the status of the corresponding receive buffer queue. if this bit is set it indicates that the corresponding receive buffer queue is locked. if the menrqaunlck bit is set in mdreg3 this bit will be auto-cleared after the user programmed delay or on receive buffer empty, otherwise, the node processor has to clear the lock by issuing a command. the auto-unlock will not work if host interface is not used to read the receive queue and the lock can be cleared only by the node processor. this feature can be enabled/disabled in memory active or initialization mode only. once enabled/disabled the feature applies to both the receive queues (if selected using mendrcv in mdreg3).
amd p r e l i m i n a r y 32 supernet 3 recv2 unlock threshold lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-5 recv1 unlock threshold figure 4. delay register (unlckdly) symbol control the supernet 3 no longer supports the ability to transmit raw symbols from the buffer memory to the phy. this feature has been removed and the mode bit symctl (bit 5, mdreg2) is now reserved and read as zero. dual attachment station (das) support the supernet 3 is a sas only device which is extensible to a das configuration. for a das implemen- tation, the mendas bit of the mdreg3 must be set and the external phy must be present. in a sas configuration, the r9:0 lines are tied to ground and x9:0 lines are driven at all times. the following configurations are supported: cfm state figure description thru_a figure 5 the internal phy is the a-port and the external phy is the b-port. the mac is placed as shown in the figure. the men- das bit in the mdreg3 must be set. wrap_a figure 6 the internal phy is the a-port and the external phy is the b-port which must be in bypass (if plc). the mac is placed as shown in the figure. the men- das bit in the mdreg3 must be set. wrap_b figure 7 the internal phy is the a-port which must be in bypass and the external phy is the b-port. the mac is placed as shown in the figure. the mendas bit in the mdreg3 must be set. wrap_s figure 8 this is the default configuration of the supernet 3. no external phy is required. the mendas bit in the mdreg3 must be reset (by default). this decouples the busses from the external phy as shown in the figure. isolated the internal phy (a-port) and the external phy (b-port) are isolated. this is the default reset state. thru_b this configuration is not supported.
p r e l i m i n a r y amd 33 supernet 3 mac rx tx rxafu 3:0, rxafl 3:0, rxafcu, rxafcl phy a phy b pdtr rx+, rxC tx+, txC supernet 3 x9:0 r9:0 19574a-6 pdtr: phy data transmit and receive functions figure 5. thru_a configuration mac rx tx rxafu 3:0, rxafl 3:0, rxafcu, rxafcl phy a phy b pdtr rx+, rxC tx+, txC supernet 3 x9:0 r9:0 19574a-7 pdtr: phy data transmit and receive functions figure 6. wrap_a configuration
amd p r e l i m i n a r y 34 supernet 3 mac rx tx rxafu 3:0, rxafl 3:0, rxafcu, rxafcl phy a phy b pdtr rx+, rxC tx+, txC x9:0 r9:0 19574a-8 pdtr: phy data transmit and receive functions supernet 3 figure 7. wrap_b configuration mac rx tx rxafu 3:0, rxafl 3:0, rxafcu, rxafcl phy a pdtr rx+, rxC tx+, txC x9:0 r9:0 19574a-9 pdtr: phy data transmit and receive functions das/sas selection mux supernet 3 figure 8. wrap_s or sas configuration changes and enhancements to phy changes from supernet 2 plc addition of scrambler/descrambler scrambler/descrambler is implemented. scrambling/ descrambling can be disabled either through a pin or through bit 0 in the plc_cntrl_c register. encoff pin function changed the function of this pin has changed slightly. in addition to turning off the encoder (as in supernet 2 plc), this pin, when asserted, now also turns off the decoder. bist enhanced the built-in self test (bist) test now covers part of the elasticity buffer and framer logic. revision identification in supernet 3 phy, bits 15:11 of the plc_status_a register will indicate 01111 on a read operation. the revision id for supernet 2 plc-s is 11111.
p r e l i m i n a r y amd 35 supernet 3 addition of scrambler/descrambler function to support copper pmd this is a description of the stream-cipher scrambler and descrambler as implemented in the physical layer controller block. the stream-cipher scrambler adds the output of a random generator to the data stream. the purpose is to spread the spectrum and reduce frequency peaks. as a result, higher signal amplitudes can be transmitted over copper that meet the requirements of the fcc and other regulatory agencies. the random generator is the polynomial 2 11 + 2 9 . the supernet 3 implementation uses a 5-bit parallel technique. the 5-bit output of the random generator is exclusive-ored with the input to produce scrambled data for transmission. the descrambler has a random generator which is identical to the random generator in the scrambler. the output of this generator is used to decipher the received scrambled data using the same exclusive-or function. since both random generators are identical, the output of the receiver random generator is the original data (data xor random ? xor random = data). this process is open loop in nature, i.e., the data has no effect on the states of the random generators. there- fore, the descrambler must incorporate synchronization circuitry to preset its state to the same state as the scrambler. once both random generators start from the same state, they will remain in synchronization. the synchronization circuitry, creg and hreg regis- ters, are designed to take advantage of the scrambled fddi line states. during the line states (hls, qls, mls and ils), creg and hreg generate known patterns. when the synchronization circuitry detects these pat- terns, it generates a capture signal and the correspond- ing output data pattern. capture controls the random generator. when it is false, the random generator operates open loop. when it is true, the random generator is preset to the deduced output data exclusive-ored with the input scrambled data. this is equal to the state of the scramblers random generator. fddi line states & detected signals line state data bits detected bits hls 00010000100 00111001110 qls 00000000000 00000000000 mls 00000000100 00000001110 ils 11111111111 11111111111 capture is enabled by sample, which is enabled by scrm_resync. scrm_resync is active when phy line state is not active line state, or unknown line state. a false scrm_resync indicates that the decoded data is correct. therefore the random genera- tor is synchronized and sample is set false. sample is set true when scrm_resync is true except during the following condition: if two consecutive idle bytes and then non-idle bytes are detected when scrm_resync is true, sample goes false and stays false for 32 rsclk cycles. after that the state of sample depends on scrm_resync. testability the test access port (tap) an ieee 1149.1 boundary-scan architecture is provided for board level testing and diagnostics. all pins are part of the boundary-scan ring except digital transmitter/ receiver pseudo-analog (pecl) pins. the tap con- sists of five pins, tck, tms, tdi, tdo and trst . these pins are dedicated connections and may not be used for any other purpose. the boundary-scan architecture includes a tap controller, an instruction register and instruction decode logic, and a test data register array. the functional description of the tap that follows is not a complete description of the ieee boundary-scan architecture. additional information and a more detailed functional description can be found in the standard document (ieee std 1149.1C1990). the description provided here covers the specifics of this particular implementation. tap controller the tap controller is a synchronous 16-state finite state machine which is driven by the tck and tms pins. all state transitions of the tap controller occur at the rising edge of tck. the transitions are based on the value of tms at the rising edge of tck. in the test-logic-reset state the instruction register is initialized with the idcode instruction. the tap controller is forced to the test-logic-reset state whenever a logic 0 is placed on the trst pin. a system reset has no effect on the tap controller.
amd p r e l i m i n a r y 36 supernet 3 instructions supported this section describes the public and private instruc- tions that are supported in this implementation. the instruction register is a 4-bit register. the least significant bit of the instruction register is the bit nearest the tdo output. the encoding of the instructions is as follows: instruction description reg. selected inst[3:0] extest external test b.s.r. 0000 idcode device identification idreg 0001 sample sample/preload b.s.r. b.s.r. 0010 tri_st force outputs to hi-z bypass 0011 runbist self-test bist execution 0101 scanbist manufacturing testing scan results 0110 bypass bypass register scan bypass 1111 extest instruction the extest instruction is used to test board level interconnect and for testing of circuitry external to supernet 3. this instruction selects the boundary scan register (bsr) for scanning between tdi and tdo when in the shift-dr controller state. during execution: 1. supernet 3 outputs are driven from the parallel data register (pdr). 2. supernet 3 internal outputs are sampled into the bsr. 3. supernet 3 inputs are sampled into the bsr. 4. supernet 3 internal inputs are driven from the parallel data register (pdr). idcode instruction the idcode instruction is provided for access to the manufacturers identity, the part number, and the version of the supernet 3. this instruction selects the 32-bit identification register for scanning between tdi and tdo in the shift-dr controller state. the idcode instruction is forced into the instruction registers parallel output latches during the test-logic-reset controller state. the 32 bits of the identification register are broken down as follows: bits description idreg[31:28] version number (initially 0001) idreg[27:12] part number - 2870 (hex) idreg[11:1] manufacturers id. the 11-bit manufacturers id. for amd is 00000000001 according to jedec publication 106-a. idreg[0] always set to logic 1. idreg[31:0] value = 1287 0003 (hex) sample instruction the sample/preload instruction is used to observe the normal operation of the supernet 3 without affecting system operation. it is also used to load values into the pdr prior to the selection of another instruction. this instruction selects the bsr for scanning between tdi and tdo during the shift-dr controller state. during execution: 1. supernet 3 outputs are driven by the supernet 3. 2. supernet 3 internal outputs are sampled into the bsr. 3. supernet 3 inputs are sampled into the bsr. 4. supernet 3 internal inputs are driven from the supernet 3 inputs. tri_st instruction the tri_st instruction is provided for easy tri-state of all supernet 3 outputs. this instruction selects the bypass register for scanning between tdi and tdo during the shift-dr controller state. runbist instruction the runbist instruction is provided for self-test of the supernet 3. this instruction must not be selected during the normal operation of the part. once the runbist instruction is selected, the bist operation is enabled by applying a minimum of 65000 tck clock cycles while in the run-test/idle tap controller state. once the minimum number of clock cycles have elapsed, proceed to load the scanbist instruction. scanbist instruction the scanbist instruction selects the bist result register for scanning between tdi and tdo during the shift-dr controller state. the bist results can be
p r e l i m i n a r y amd 37 supernet 3 shifted out in the shift_dr tap controller state. the bist result register is 33 bits in length. bypass instruction the bypass instruction is used to bypass the super- net 3 bsr and shorten access times to other devices on a board. this instruction selects the bypass register for scanning between tdi and tdo during the shift-dr controller state. the supernet 3 is not otherwise affected by this instruction. boundary scan cells in boundary scan most of the chip input and output latches are linked together to form a scan chain. the main purpose of this is for board level testing. the boundary scan ring order is listed in the following table. bsr cell no. pin no. pin type description 1 54 input scrm 2 55 input encoff 3 56 output ebferr 4 67 output fotoff 5 68 output ulsb 6 69 output lsr[2] 7 70 output lsr[1] 8 71 output lsr[0] 9 72 input rpar 10 73 input r[0] 11 74 input r[1] 12 75 input r[2] 13 77 input r[3] 14 78 input r[4] 15 79 input r[5] 16 80 input r[6] 17 81 input r[7] 18 82 input rcl 19 83 input rcu 20 84 input flxi 21 n/a C oe control (1 to enable) 22 86 output xpar 23 87 output x[0] 24 88 output x[1] 25 89 output x[2] 26 90 output x[3] 27 91 output x[4] 28 92 output x[5] 29 93 output x[6]
amd p r e l i m i n a r y 38 supernet 3 bsr cell no. pin no. pin type description 30 94 output x[7] 31 95 output xcl 32 96 output xcu 33 98 output xs[0] 34 99 output xs[1] 35 100 output xs[2] 36 101 output xs[3] 37 102 output rs[0] 38 103 output rs[1] 39 106 output rs[2] 40 107 output rs[3] 41 108 output rs[4] 42 109 output rs[5] 43 111 input xsa_xact 44 112 input xsamat 45 113 input xda_xact 46 114 input xdamat 47 116 output rxafcu 48 n/a C oe control (1 to enable) 49, 50 117 inout rxafl 51 118 output rxafu[3] 52 120 output rxafu[2] 53 121 output rxafu[1] 54 122 output rxafu[0] 55, 56 123 inout rxafl[3] 57, 58 124 inout rxafl[2] 59, 60 125 inout rxafl[1] 61, 62 126 inout rxafl[0] 63, 64 128 inout bdtag 65, 66 129 inout bdp[0] 67, 68 130 inout bdp[1] 69, 70 131 inout bdp[2] 71, 72 133 inout bdp[3] 73, 74 134 inout bd[31] 75, 76 135 inout bd[30] 77, 78 136 inout bd[29] 79, 80 138 inout bd[28] 81, 82 139 inout bd[27] 83, 84 140 inout bd[26]
p r e l i m i n a r y amd 39 supernet 3 bsr cell no. pin no. pin type description 85, 86 142 inout bd[25] 87, 88 143 inout bd[24] 89, 90 145 inout bd[23] 91, 92 146 inout bd[22] 94 147 inout bd[21] 95, 96 148 inout bd[20] 97, 98 150 inout bd[19] 99, 100 151 inout bd[18] 101, 102 152 inout bd[17] 103, 104 153 inout bd[16] 105 154 output cso 106 155 output wr 107 n/a C oe control (1 to enable) 108 158 output rd 109, 110 159 inout bd[15] 111, 112 160 inout bd[14] 113, 114 161 inout bd[13] 115, 116 162 inout bd[12] 117, 118 163 inout bd[11] 119, 120 164 inout bd[10] 121, 122 165 inout bd[9] 123, 124 166 inout bd[8] 125, 126 168 inout bd[7] 127, 128 169 inout bd[6] 129, 130 170 inout bd[5] 131, 132 171 inout bd[4] 133, 134 173 inout bd[3] 135, 136 174 inout bd[2] 137, 138 175 inout bd[1] 139, 140 176 inout bd[0] 141 178 output rdata2 142 179 output rdata1 143 180 input hsreq[2] 144 181 input hsreq[1] 145 182 input hsreq[0] 146 183 output hsack 147 185 output qctrl[2] 148 186 output qctrl[1] 149 187 output qctrl[0] 150 n/a C oe control (1 enable)
amd p r e l i m i n a r y 40 supernet 3 bsr cell no. pin no. pin type description 151 189 output addr[0] 152 190 output addr[1] 153 191 output addr[2] 154 192 output addr[3] 155 194 output addr[4] 156 195 output addr[5] 157 196 output addr[6] 158 197 output addr[7] 159 199 output addr[8] 160 200 output addr[9] 161 201 output addr[10] 162 202 output addr[11] 163 204 output addr[12] 164 205 output addr[13] 165 206 output addr[14] 166 207 output addr[15] 167, 168 2 inout np[15] 169, 170 3 inout np[14] 171, 172 4 inout np[13] 173, 174 5 inout np[12] 175, 176 6 inout np[11] 177, 178 7 inout np[10] 179, 180 9 inout np[9] 181, 182 10 inout np[8] 183, 184 11 inout np[7] 185, 186 13 inout np[6] 187, 188 14 inout np[5] 189, 190 15 inout np[4] 191, 192 16 inout np[3] 193, 194 17 inout np[2] 195, 196 18 inout np[1] 197, 198 19 inout np[0] 199 n/a C oe control (1 to enable) 200 21 output mintr1 (oecell -1 to force 0, 0 to disable) 201 22 output mintr2 (oecell -1 to force 0, 0 to disable) 202 23 output mintr3 (oecell -1 to force 0, 0 to disable) 203 24 output mintr4 (oecell -1 to force 0, 0 to disable) 204 25 input bmclk 205 27 input bclk 206 29 input npmemrq
p r e l i m i n a r y amd 41 supernet 3 bsr cell no. pin no. pin type description 207 30 output npmemack 208 32 output ready (oecell C1 to force 0, 0 to disable) 209 33 input r/ w 210 34 input ds 211 35 input csi 212 36 input lsclk 213 37 input npa[7] 214 38 input npa[6] 215 39 input npa[5] 216 40 input npa[4] 217 41 input npa[3] 218 42 input npa[2] 219 43 input npa[1] 220 44 input npa[0] 221 45 input npmode 222 46 input rst built-in self test (bist) the bist feature of the supernet 3 is provided to ease board and system level testing, as well as our own manufacturing testing. this feature can be accessed through the tap as well as the system interface. it is expected that board level testing will use the tap interface, while system level testing will not have access to the tap interface and will need to run bist through the system interface. there are two functional units in the supernet 3 that are tested with bist. these are the af cam core and the enhanced phy. the bist testing of the two functional units is available through the node processor interface. see the af specification for a description of how to run the bist for the af. the enhanced phy bist is run using the phy bist access as described in the supernet 2 plc data sheet. function bist signature (hex) internal plc bist 5b6b address filter bist 0553 scanbist 1 5b6b 0553 discry function no longer supported setting the discry bit in mode register 1 (mdreg1, bit 6) permitted testing the operation of certain internal timers such as trt, tht, tvx, and tmsync by breaking them into smaller segments. with the enhanced testability features of supernet 3, the discry function is no longer provided. the bit 6 of mode register 1 (mdreg1) is reserved and shall return a value of zero when read. summary of changes to status and mode registers the following is the summary of changes. the bits in the register which are shaded indicate change from supernet 2. all reserved bits shall be read as zero except where noted.
amd p r e l i m i n a r y 42 supernet 3 lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-10 stefrms stefrma1 reserved reserved reserved stecmda1 reserved stexdons stbfla stbfls stxabrs stxabra0 stxabra1 reserved sxmtabt stefrma0 reserved bits are read as zero unless otherwise stated. figure 9. status register 1 C upper 16 bits (st1u) (npaddr = 00h) lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-11 sqlcks sqlcka1 reserved reserved reserved reserved reserved spcepds spcepda0 spcepda1 reserved stburas stbura0 stbura1 reserved sqlcka0 reserved bits are read as zero unless otherwise stated. figure 10. status register 1 C lower 16 bits (st1l) (npaddr = 01h)
p r e l i m i n a r y amd 43 supernet 3 lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-12 sotrbec sbec sloclm shiclm smyclm sclm serrsf snfsld reserved reserved srcvovr srbfl srabt srbmt srcomp smybec reserved bits are read as zero unless otherwise stated. figure 11. status register 2 C upper 16 bits (st2u) (npaddr = 02h) lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-13 srngop stkerr stkiss stuxexp strtexp smisfrm sadet sphinv slstctr serrctr sfrmctr ssifg sdupclm strtexr sestriptk smultda reserved bits are read as zero unless otherwise stated. figure 12. status register 2 C lower 16 bits (st2l) (npaddr = 03h)
amd p r e l i m i n a r y 44 supernet 3 lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-14 hoflxi0 full/half locktx exgpa0 exgpa1 discry selra addet0 addet1 addet2 selsa mmode0 mmode1 mmode2 snglfrm hoflxi1 reserved bits are read as zero unless otherwise stated. figure 13. mode register 1 (mdreg1) (npaddr = 10h) lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-15 afull0 afull2 afull3 rcverr reserved synprq ennprq enhsrq rxfbb0 rxfbb1 lsb parity chkpar strpfcs rcvmode afull1 reserved bits are read as zero unless otherwise stated. figure 14. mode register 2 (mdreg2) (npaddr = 20h)
p r e l i m i n a r y amd 45 supernet 3 status register 3 (st3u & st3l) a 32-bit read only register, designated st3, and a 32 bit read/write register, designated imsk3, has been added in supernet 3. this register is dedicated to status handling and interrupt reporting. any of the bits in this status register can be used generate an interrupt. the bits in st3 may be masked by the interrupt mask registers (imsk3) for complete control of the interrupt conditions. st3 has status bits associated with receive operation for recv2 queue, status of internal cam match operation, and bist operation for the various sub-blocks of the supernet 3. all status bits except srbmt2 and srbfl2 are auto-cleared on reading the register. the remaining bits are set/reset depending upon the state of the monitored conditions. refer to interrupt mechanisms for more detailed information regarding interrupt handling. lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-16 srqunlck1 srperrq1 srperrq2 reserved reserved reserved reserved reserved reserved reserved srcvovr2 srbfl2 srabt2 srbmt2 srcomp2 srqunlck2 figure 15. status register 3 C upper 16 bits (st3u) (npaddr = 61h)
amd p r e l i m i n a r y 46 supernet 3 af_bist_done plc_bit_done lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-17 reserved reserved sicamdamat sicamdaxact sicamsamat sicamsaxact reserved reserved reserved reserved reserved reserved reserved reserved figure 16. status register 3 C lower 16 bits (st3l) (npaddr = 62h) the following bits are in st3u (the upper half of st3). status receive complete (receive queue 2) srcomp2 (bit 15) this bit is set at the completion of a frame reception following the writing of the frame status and length. receive frames that are aborted set this bit, but flushed frames do not. this is valid in tag and modified tag mode. status receive buffer empty (receive queue 2) srbmt2 (bit 14) this bit is set when the receive buffer is empty (i.e. rpr2 = wpr2 after an increment of rpr), and is reset when frames are in the receive buffer. this bit is not auto-cleared when read. an interrupt is generated due to setting of this bit when read from the receive queue is attempted while the receive buffer is empty. status receive abort (receive queue 2) srabt2 (bit 13) the srabt2 bit is set when the frame being received is aborted. frames that normally would be flushed but are aborted due to threshold criterion in tag mode would set this bit. status receive buffer full (receive queue 2) srbfl2 (bit 12) this bit is set when the receive buffer is full (rpr2 = wpr2 after an increment of wpr2). the buffer-mem- ory receive queue is then locked for further input. srbfl2 can be cleared using the clear receive queue lock (20h) or clear all queue locks (3fh) commands, or by using the auto-unlock feature. status receive fifo overflow (receive queue 2 ) srcvovr2 (bit 11) this bit when set, indicates that the supernet 3 receive 2 fifo has overflowed and receive data has been lost. this condition may occur during the receive buffer full state. supernet 3 will not set the frame- status c indicator (frame copied) on repeated frames when this bit is set. reserved (bit 10Cbit 4) these bits are reserved for future use. some of these reserved bits may read zero or one and the user should ignore these bits. the corresponding mask register bits should be programmed to mask out the interrupts from these bits.
p r e l i m i n a r y amd 47 supernet 3 status receive parity error queue 2 srperrq2 (bit 3) this bit is set when there is parity error in the data received in queue 2. status receive parity error queue 1 srperrq2 (bit 2) this bit is set when there is parity error in the data received in queue 1. status receive queue 2 unlocked srqunlck2 (bit 1) this bit is set when the auto-unlock feature unlocks the receive queue 2 lock due to buffer full condition. once the unlock threshold is crossed due the host read operation, the supernet 3 will clear the lock on the receive queue 2 and enable the queue for further input. status receive queue 1 unlocked srqunlck2 (bit 0) this bit is set when the auto-unlock feature unlocks the receive queue 1 lock due to buffer full condition. once the unlock threshold is crossed due the host read operation, the supernet 3 will clear the lock on the receive queue 1 and enable the queue for further input. the following bits are in st3l (the lower half of st3). reserved (bit 15Cbit 8) these bits are reserved for future use. some of these reserved bits may read zero or one and the user should ignore these bits. the corresponding mask register bits should be programmed to mask out the interrupts from these bits. status internal cam source address exact match. sicamsaxact (bit 7) this bit when set indicates that the source address of the incoming frame exactly matches an entry in the internal cam. this bit is useful for monitoring frame reception and internal cam operation. status internal cam source address match sicamsamat (bit 6) this bit when set indicates that the source address of the incoming frame matches an entry in the internal cam based on the internal cam match logic. this bit is useful for monitoring frame reception and internal cam operation. status internal cam destination address exact match sicamdaxact (bit 5) this bit when set indicates that the received frame da exactly matches an entry in the internal cam. this bit is useful for monitoring frame reception and internal cam operation. status internal cam destination address match sicamdamat (bit 4) this bit when set indicates that the received frame da matches an entry in the internal cam based in the internal cam match logic. this bit is useful for monitoring frame reception and internal cam operation. reserved (bit 3) this bit is reserved for future use. the bit may read zero or one and the user should ignore this bit. the corresponding mask register bit should be programmed to mask out the interrupts from this bit. reserved (bit 2) this bit is reserved for future use. the bit may read zero or one and the user should ignore this bit. the corresponding mask register bit should be programmed to mask out the interrupts from this bit. status physical layer controller bist done plc_bist_done (bit 1) this bit when set indicates that the plc bist is complete. status address filter bist done af_bist_done (bit 0) this bit when set indicates that address filter (internal cam) bist is complete.
amd p r e l i m i n a r y 48 supernet 3 rpx2 swpx2 wpr2 rpxa1 swpxa1 wpxa1 rpxa0 swpxa0 wpxa0 rpxs swpxs wpxs rpr1 swpr1 wpr1 sacl sabc eacb earv1 eas eaa0 eaa1 earv2 special frame area receive queue 1 synchronous queue (transmit) asynchronous queue 0 (transmit) asynchronous queue 1 (transmit) receive queue 2 19574a-18 figure 17. buffer memory queue organization parity generation and checking the supernet 3 will have the following sequence of parity generation and checking: transmit path: the parity, (even or odd) will be checked at the buffer memory interface (bdp pins). even parity will be regenerated at the macexternal phy interface. receive path: parity (even or odd) will be generated at the buffer memory interface. even parity will be checked at the external phy (r bus) interface, if ena_par_chk (bit 10) in plc_cntrl_a register is set. node processor synchronous mode operation the npmode pin (external pin) must be strapped high to select supernet 3 synchronous operation and strapped low to select supernet 3 asynchronous operation. there are two possible methods of synchronous operation of the supernet 3: 1. bmclk frequency equals bclk frequency. (i.e. 12.5 mhz), and both clocks must be in phase. 2. bmclk operates at twice bclk (i.e. bmclk = 25 mhz), and both clocks must be in phase.
p r e l i m i n a r y amd 49 supernet 3 in either method, the ds is ignored and should be inactive (high) during all synchronous accesses. the read cycle is initiated by asserting the csi , npaddr, nprw signal which is sampled by the rising edge of the clock. the nprw signal should be high for read and low for write. at least one clock cycle after the sampling edge, the supernet 3 will begin to drive the np bus, and this allow the chip driving the np bus in the previous read or write cycle time to tristate the np bus. after the next rising edge of clock (the second rising edge after the assertion of csi ) the data on the np bus will be valid and the ready signal will be asserted. the data will remain valid until the second rising edge of clock after the de-assertion of csi . the supernet 3 will tristate the np bus within 1/2 clock cycle after this clock edge. regardless of how many clock cycles are needed for executing any supernet 3 instruction, ready stays active only for one clock cycle. a write cycle is very similar to the read cycle. the principal difference are as follows: 1. the nprw signal must be low while csi is asserted. 2. the data written must be valid on the second rising edge of clock after csi is asserted and remain valid until the next rising edge of the clock and ready signal goes active (i.e. low). regardless of how many clock cycles are needed for executing any supernet 3 instruction, ready stays active only for one clock cycle. the node processor must tristate the np bus within one half clock period after the second rising edge after the assertion of csi . the node processor can extend the write cycle and the time it has to tristate the np bus by delaying the de-assertion of csi signal. all register access is complete in two cycles and ready is asserted at the positive edge of the second clock cycle. an exception is for mdr accesses that may take more than two clock cycles, at which point the assertion of ready is deferred until the last clock period of the execution cycle. regardless of how many clock cycles are needed for executing any supernet 3 instruction, ready stays active only for one clock cycle. refer to timing diagrams in specifications for details. the assertion of ready signal could be delayed during mdr accesses by n multiples of clock period. address filter (af) support xda _ xact and xsa _ xact input signals are provided for the external cam. xda_xact external destination address exact match (input, active low) this input indicates whether the external address match was exact (low) or inexact (high). this input should remain asserted for at least one bclk cycle, and must be deasserted for at least one bclk cycle before a subsequent external source address match is recog- nized. it must be asserted and deasserted in an identical fashion to the xdamat pin. this input is used in conjunction with the xdamat pin as follows: match action xda _ xact and xdamat a, c indicators set and frame copied*. xda _ xact and xdamat invalid combination. ignored by mac. xda_xact and xdamat a, c indicators not set and frame copied. xda_xact and xdamat no action. *frame is copied if valid frame or if in promiscuous or limited promiscuous mode. in osm, the a, c indicators are set ac- cording to the osm rules if both bit 4 and bit 5 (meind0,1) of mdreg3 are not set. the xda_xact pin, which is generated by the external af, is logically ored with the af_dax output signal generated by the internal af logic. this pin is enabled only if the menxact bit in the mode register 3 (mdreg3) is set. this pin should be tied high (v cc ) when external address detection (an external af) is not used. xsa _ xact external source address exact match (input, active low) this input indicates whether the external source ad- dress match was exact (low) or inexact (high). this input should remain asserted for at least one bclk cycle, and must be deasserted for at least one bclk cycle before a subsequent external source address match is recog- nized. it must be asserted and deasserted in an identical fashion to the xsamat pin. this input is used in conjunction with the xsamat pin as follows: match action xsa _ xact and xsamat frame stripped. xsa _ xact and xsamat invalid combination. ignored by mac. xsa_xact and xsamat frame not stripped. xsa_xact and xsamat no action. the xsa_xact pin which is generated by the external af is logically ored with the af_sax output signal generated by the internal af logic. this pin is enabled only if the menxact bit in the mode register 3 (mdreg3) is set. this pin should be tied high (v cc ) when external address detection (an external af) is not used. introduction the address filter (af) is a functional block that extends the group and/or individual mac address recognition capabilities of the core fddi mac. the af
amd p r e l i m i n a r y 50 supernet 3 recognizes both source and destination addresses, extending the strip and copy functions of the core fddi mac. the af is a content addressable memory (cam) that contains 32 entries. each entry consists of a 48-bit comparand, a 48-bit mask and a 6-bit personality. the comparand holds the mac addresses (individual and/or group addresses) for which to look in frames received by the mac. the mask identifies those bits that are to participate in the address comparison. the personality holds information pertaining to the comparand such as its validity, whether it is a source or destination address, and whether a match by this comparand is to be considered exact. the af provides quasi-parallel operation, allowing simultaneous manipulation of the cam from the node processor interface and address matching from the fddi mac receive bus interface. the af receives a byte-wide data stream from the fddi mac receive bus as well as the necessary control information to identify the location of the source and destination addresses in the byte stream. it provides an indication of source and destination match and exact match to the fddi mac. the af also has a 16-bit wide interface to the node processor bus. this interface allows the node processor access to the af data registers and the command and status registers. function of the address filter the af performs the function of matching source and destination addresses presented on the receive data bus and indicating such matches to the mac. the mac uses this information in such decisions as stripping frames, copying frames and setting frame status indicators. the af also matches addresses presented through the node processor interface and indicates these matches in the status register. this allows the node processor to efficiently manage the contents of the af. to perform the function of matching addresses from the receive data bus, the af loads bytes from the receive data bus into a comparand register. the mac indicates the bytes to be loaded. once the af receives this indication from the mac, the af loads six consecutive bytes into the comparand register. upon loading the comparand register, the af performs a parallel compari- son of all the valid cam entries in the af with the comparand register. the af then indicates the result of this comparison to the mac. during af address comparision operation from the received data bus, the node processor interface operations are ignored, and the error bit, along with the done bit, is set in the status register. to perform the function of matching addresses from the node processor interface, the node processor loads six bytes of information, two bytes at a time, into the node processor comparand registers. the node processor then issues a command to the af to perform the comparison operation. the af ensures that the node processor commanded comparison does not interfere with a comparison from the mac receive data bus. the af indicates the result of the comparison to the node processor in the status register. to perform any comparison operations, comparands must be written into the cam of the af. the node processor performs this operation. writing a comparand to the cam in the af is done by loading the new comparand into the node processor comparand regis- ters. the node processor then loads a 48-bit mask associated with this comparand by loading the mask into the node processor mask registers. finally, the node processor loads the personality associated with this comparand by loading the node processor person- ality register. the node processor now completes the operation by issuing a command to write into the cam through the command register. the status register reflects the current state of the operation, indicating when the af is busy or full. once completed, the comparand is available for comparison operations through both the node processor and mac receive bus interfaces. additional comparands may be loaded by repeating this operation until no empty locations remain in the cam. the af also provides a mechanism to remove entries from the cam. this process is called invalidation. to invalidate an entry in the af, the node processor will load the contents of the cam that are to be invalidated into the node processor comparand registers. the node processor then issues an instruction to find the entry in the cam through the command register. when it is determined that the entry that has been found is the one to be deleted, the node processor issues a command to invalidate the entry. since it is possible that more than one entry in the af may match the comparand, the af indicates when a multiple match occurs. when this occurs, the node processor may temporarily prevent an entry in the af from participating in find commands issued by the node processor until the correct entry is found. the status register indicates when the af is not busy, i.e., when operations are complete. there is one more function of the af that allows the entire cam to be invalidated in a single operation. the node processor may issue an instruction to invalidate the entire cam through the command register. node processor registers there are ten registers in the node processor interface of the af. they are the command register, the status register, the built-in self test signature register, the personality register, three comparand registers and three mask registers.
p r e l i m i n a r y amd 51 supernet 3 command register (afcmd) the command register is a 16-bit register that may be read and written through the node processor interface. writing to this register causes the af to perform the commanded operation. all data necessary for an operation must be set up in the appropriate registers before the command being issued for an operation. this register will be cleared (filled with zeroes) on a reset and will retain its data after each time it is written until the next reset. lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-19 inst(0) inst(1) inst(2) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved figure 18. command register reserved (bits 15:3) reserved these bits are reserved for future use. these bits will always read back as zeroes. inst (bits 2:0) instruction these bits are the encoded instructions to the af. when these bits are written, the af is commanded to perform the associated function. the encoding of the instruc- tions is presented in the table below. these bits will read back the last data that was written to this register.
amd p r e l i m i n a r y 52 supernet 3 inst 2:0 function 000 invalidate cam: this function invalidates all entries in the cam. the done, full, found, mult, error, bistdone and exact bits in the status register will be cleared when this com- mand is issued. the done and empty bits in the status register will be set upon completion of this operation. 001 write cam: this function writes the contents of the comparand, mask and personality registers into an empty location in the cam. the done, full, found, mult, bistdone and exact bits in the status register will be cleared when this command is issued. the done bit in the status register will be set upon completion of this operation. the full bit in the status register will be set if the cam is full when this operation is completed. if the full bit is set when this command is issued, the write operation will not be performed and the error bit in the status register will be set. otherwise, the error bit will be cleared. 010 read cam: this function causes the contents of the cam entry matching the comparand (indi- cated by the found bit in the status register after a find command) to be written to the comparand, mask and personality registers in the node processor interface. if more than one entry matches the comparand (indicated by the mult bit in the status register), one of the entries will be chosen arbi- trarily. the done, found, mult, error, bistdone and exact bits in the status register will be cleared when this command is issued. upon completion of this operation, the done bit in the status register will be set. the error bit will be set if this operation is attempted while the cam is empty or if the found bit is not set. 011 run bist: this function causes the af to initiate its built-in self test. the contents of the cam, in- cluding all of its registers, may be modified by the operation of this self test. the done, found, mult, error, bistdone and exact bits in the status register will be cleared when this com- mand is issued. upon completion of this operation, the done and bistdone bits in the status reg- ister will be set. other status bits may be in arbitrary states. the af must be reset after bist is com- pleted to return it to a known state before performing any other operations on the af. 100 find: this function causes the af to perform a parallel comparison of the comparand registers with the contents of the cam. cam entries that have the skip bit set will not match the comparand. the node processor mask registers do not participate in this operation. the done, found, mult, er- ror, bistdone and exact bits in the status register will be cleared when this command is is- sued. upon completion of this operation, the done bit in the status register will be set and the found, mult and exact bits will be updated with the appropriate status of the operation. 101 invalidate: this function operates on the result of the last find instruction, above, and sets the invalid bit in the personality of the first matching entry in the cam. the done, found, mult, error, bistdone and exact bits in the status register will be cleared when this command is issued. upon completion of this operation, the done bit in the status register will be set. the empty bit will be updated with the appropriate status after the operation. the error bit will be set if this operation is attempted while the found bit is not set. otherwise, the error bit will remain cleared. 110 skip: this function operates on the result of the latest find operation and causes the af to set the skip bit in the personality of the first matching cam entry. the skip bit will be set in the same entry that will be read by issuing a read cam instruction. the done, found, mult, error, bistdone and exact bits in the status register will be cleared when this command is issued. upon completion of this operation, the done bit in the status register will be set. the error bit will be set if this operation is attempted while the found bit is not set. otherwise, the error bit will remain cleared. 111 clear all skip bits: this function causes the cam to clear all skip bits. the done, found, mult, error, bistdone and exact bits in the status register will be cleared when this com- mand is issued. upon completion of this operation, the done bit in the status register will be set.
p r e l i m i n a r y amd 53 supernet 3 status register (afstat) the status register is a 16-bit register that may be read and written through the node processor interface. this register contains the status of the af. all bits of the status register are static; they are not cleared after a read operation. lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-20 reserved reserved rev. number 0 rev. number 1 rev. number 2 bistdone empty error mult exact found full done reserved reserved reserved reserved bits are read as zero unless otherwise stated. figure 19. status register done (bit 15) done indicator the done bit indicates to the node processor that the af is finished performing a previously commanded operation. the node processor must not issue any command to the af when this bit is not set. this bit may be used to generate an interrupt to the node processor indicating the completion of an operation. full (bit 14) cam full this bit indicates the state of the cam array. when this bit is set, there are no invalid cam entries, i.e., all cam entries have their valid bit set. when this is reset, there is at least one invalid entry in the cam. if this bit is set, the af should not be commanded to write cam. if that instruction is issued when this bit is set, the operation will not be performed. note: the error bit in the status register will not be set if a write cam instruction is issued when this bit is set. the user has to read this bit status before attempt- ing to write an entry into the cam. found (bit 13) comparand found in cam this bit indicates the result of a find operation. when set, this bit indicates that the data in the comparand register matches at least one entry in the cam (as masked by the mask entries). if this bit is reset, this bit indicates that no entry in the cam matches the data in the comparand register. this bit is cleared as a result of a skip or invalidate operation. exact (bit 12) exact match this bit reflects the result of a find operation. when set, this bit indicates that at least one matching cam entry (as masked by its mask entry) has the dax bit set in its personality byte. if this bit is reset, no matching cam entries have the dax bit set in the corresponding personality bytes. this bit is cleared as a result of a skip or invalidate operation.
amd p r e l i m i n a r y 54 supernet 3 mult (bit 11) multiple match this bit reflects the result of a find operation. this bit has meaning only if the found bit is set. if this bit is set, it indicates that more than one entry in the cam matches the value in the node processor comparand register. this bit is cleared as a result of a skip or invalidate operation. error (bit 10) error this bit indicates that an improper operation was attempted. this bit will be set for the following condtions: if an attempt is made to issue the read cam instruction while the empty bit is set. if the invalidate or skip instructions are issued and the found bit is not set. if the node processor command operation is ignored due to receive bus address match operation. empty (bit 9) cam empty this bit reflects the state of the cam array. this bit will be set if all entries in the cam have their valid bits reset. empty bit will be reset after write cam command. bistdone (bit 8) bist complete this bit reflects the state of the built-in self test (bist). this bit will be cleared after reset, while bist is running and after an instruction is issued to the command register. it will be set once bist is complete. revision number bits 7, 6 and 5 provide a three-bit binary value that indicates the revision number of the address filter. reserved (bits 4:0) reserved these bits are reserved for future use. these bits should always be written with zeroes to ensure compatibility with future revisions of the af. these bits will always read back as zeroes. bist signature register (afbist) this is a 16-bit register that may be read and written by the node processor. after the initiation of bist, this register will hold the signature resulting from the execution of built-in self test when the bistdone bit is set in the status register. comparand registers (afcomp2:0) the comparand registers are 16-bit registers that may be read and written by the node processor. afcomp0 corresponds to bits 15:0 of the cam entry. afcomp1 corresponds to bits 31:16 of the cam entry. afcomp2 corresponds to bits 47:32 of the cam entry. this register will be cleared (filled with zeroes) on a reset and will retain its data after each time it is written until the next reset. this register will be updated with the contents of the first matching entry in the cam if a read cam instruction is issued to the command register while the found bit is set. fc da (47:32) da (31:16) da (15:0) sa afcomp2 afcomp1 afcomp0
p r e l i m i n a r y amd 55 supernet 3 lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-21 afcomp(32) afcomp(33) afcomp(34) afcomp(35) afcomp(36) afcomp(37) afcomp(38) afcomp(39) afcomp(40) afcomp(41) afcomp(42) afcomp(43) afcomp(44) afcomp(45) afcomp(46) afcomp(47) figure 20. node processor comparand register (afcomp2) lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-22 afcomp(16) afcomp(17) afcomp(18) afcomp(19) afcomp(20) afcomp(21) afcomp(22) afcomp(23) afcomp(24) afcomp(25) afcomp(26) afcomp(27) afcomp(28) afcomp(29) afcomp(30) afcomp(31) figure 21. node processor comparand register (afcomp1)
amd p r e l i m i n a r y 56 supernet 3 lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-23 afcomp(0) afcomp(1) afcomp(2) afcomp(3) afcomp(4) afcomp(5) afcomp(6) afcomp(7) afcomp(8) afcomp(9) afcomp(10) afcomp(11) afcomp(12) afcomp(13) afcomp(14) afcomp(15) figure 22. node processor comparand register (afcomp0) mask registers (afmask2:0) the mask registers are 16-bit registers that may be read and written by the node processor. afmask0 corre- sponds to bits 15:0 of the cam mask entry. afmask1 corresponds to bits 31:16 of the cam mask entry. afmask2 corresponds to bits 47:32 of the cam mask entry. a 1 written to a bit position in the mask register will enable the corresponding bit in the comparand to participate in the comparison operation. a 0 written to a bit in the mask register will disable, or mask, the corresponding bit in the comparand. a bit that is masked will always match the corresponding bit in a comparison operation. this register will be cleared (filled with zeroes) on a reset and will retain its data after each time it is written until the next reset. this register will be updated with the contents of the first matching entry in the cam if a read cam instruction is issued to the command register while the found bit is set.
p r e l i m i n a r y amd 57 supernet 3 lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-24 afmask(32) afmask(33) afmask(34) afmask(35) afmask(36) afmask(37) afmask(38) afmask(39) afmask(40) afmask(41) afmask(42) afmask(43) afmask(44) afmask(45) afmask(46) afmask(47) figure 23. mask register (afmask2) lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-25 afmask(16) afmask(17) afmask(18) afmask(19) afmask(20) afmask(21) afmask(22) afmask(23) afmask(24) afmask(25) afmask(26) afmask(27) afmask(28) afmask(29) afmask(30) afmask(31) figure 24. mask register (afmask1)
amd p r e l i m i n a r y 58 supernet 3 lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-26 afmask(0) afmask(1) afmask(2) afmask(3) afmask(4) afmask(5) afmask(6) afmask(7) afmask(8) afmask(9) afmask(10) afmask(11) afmask(12) afmask(13) afmask(14) afmask(15) figure 25. mask register (afmask0) personality register (afpers) the personality register is a 16-bit register that may be read and written by the node processor. this register will be cleared (filled with zeroes) on a reset and will retain its data after each time it is written until the next reset. this register will be updated with the contents of the first matching entry in the cam if a read cam instruction is issued to the command register while the found bit is set.
p r e l i m i n a r y amd 59 supernet 3 lsb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574a-27 valid dax sa sax skip reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved da reserved bits are read as zero unless otherwise stated. figure 26. personality register reserved (bits 15:6) reserved these bits are reserved for future use. these bits should always be written with zeroes to ensure compatibility with future revisions of the af. these bits will always read back as zeroes. skip (bit 5) skip this entry this bit prevents the associated entry from indicating a match during a find operation begun through the command register. this bit has no effect on compari- sons with comparands received from the mac interface. sax (bit 4) source address exact this bit causes the af to indicate that any comparison matching this cam entry to a source address will be indicated as being an exact match. an exact match may contain masking done while comparing the entry. invalid if sa is zero. sa (bit 3) source address this bit enables the cam entry for comparison with source addresses. dax (bit 2) destination address exact this bit causes the af to indicate that any comparison matching this cam entry to a destination address will be indicated as being an exact match. an exact match may contain masking done while comparing the entry. invalid if da is zero. da (bit 1) destination address this bit enables the cam entry for comparison with destination addresses. valid (bit 0) cam entry valid this bit indicates that the cam entry is valid and is enabled for comparisons with addresses indicated by the sa and da bits.
amd p r e l i m i n a r y 60 supernet 3 node processor register address map the registers accessible through the node processor interface are addressed as shown in the table below. register mnemonic address register name afcmd b0 address filter command register afstat b2 address filter status register afbist b4 address filter bist signature afcomp2 b6 address filter comparand 2 register afcomp1 b8 address filter comparand 1 register afcomp0 ba address filter comparand 0 register afmask2 bc address filter mask 2 register afmask1 be address filter mask 1 register afmask0 c0 address filter mask 0 register afpers c2 address filter personality register mac interface the af interfaces to the fddi mac through the receive data bus, mac status and control signals, and the af match output signals. as described above, the af loads addresses to be compared as they are received from the network. the mac signals the af at the beginning of the source and/or destination address through the mac address state machines state variable. the af uses this state variable to load six consecutive bytes into the mac comparand register and perform the comparison of the address against the contents of the cam when the complete address is in the register. the af signals the mac with the result of the comparison and if the comparison is exact (as determined by the appropriate bit in the personality byte). the af will decode the frame control (fc) field of the received frame and will not participate in the address match if bit 6 of the fc is zero (indicating a short address frame). mac comparand register this is a 48-bit register that is loaded from the mac receive data bus. the data arrives one byte at a time and is loaded byte serially into the register. an internal multiplexer is driven by the state variable of the mac address state machine. once started, the state machine causes the register to load six consecutive bytes from the receive data bus into the comparand register. upon completion of the loading of the register, the contents will be transferred to the mac comparand shadow register for comparison with the contents of the cam. mac comparand shadow register the mac comparand shadow register receives the contents of the mac comparand register once that register has been loaded with six bytes of address information from the mac receive data bus. this allows the mac comparand register to immediately begin loading a subsequent address from the receive data bus without interfering with the comparison function of the af. once data has been transferred into the mac comparand shadow register, the contents of the shadow register are compared with the contents of the cam.
p r e l i m i n a r y amd 61 supernet 3 19574a-28 bclk rx cmrx_rbus cmrx_addrsm_state cmrx_startdelimeter_rx cmrx_da_next_done cmrx_sa_next_done af_da_match af_dax af_sa_match af_sax figure 27. afCmac interface handshake (internal signals)
amd p r e l i m i n a r y 62 supernet 3 address filter test specification introduction the address filter (af) core requires a special set of test patterns to provide adequate fault coverage. the mask and data bits of the af are similar to an sram cell and must be tested with the types of test patterns that are used to test srams. the main fault models that are applied in sram testing are the stuck-at fault model, the transition fault model, and the coupling fault model. the stuck-at fault model describes the condition where a cell or line is always 0 or 1 and cant be changed to the opposite state. the transition fault model describes the condition where a cell or line fails to undergo a transition from 0_1 or from 1_0 when it is written. the coupling fault model describes the condition where a write to a cell that causes a transition in that cell, also causes a transition in another cell. in addition to the test necessary for the above fault models, the cam contains additional personality bits, match logic and a priority encoder that must also be tested. the af core will be tested through the use of built-in self test (bist). the patterns that need to be applied to the sram portion of the cam are algorithmic in nature and can be easily implemented with bist. the components of the af bist logic will include a state machine, a data generator, a signature register, and an address generator. test logic description this section provides a description of the af test logic. bist operation the bist feature can be accessed by one of two methods. the first means of access is a serial mode of access meant to be used with an ieee 1149.1 test access port (tap) controller. the second means of access is a parallel mode of access using the node processor interface. each means of access is described further below. tap interface access to bist through the tap interface is provided so that the core can be tested in a product that supports the runbist instruction of the ieee 1149.1 standard. as such, the implementation of the bist should conform to all the rules described for the runbist instruction in the standard. some of these rules apply only to the design of the tap controller itself, while others affect the implementation of the af bist logic. the rules that affect the implementation of the af bist logic are summarized below. the af will have a serial input and serial output through which the results of the bist can be shifted. these resuls shall be shifted in response to the appropriate tap interface signals. the af bist execution will depend on signals provided by the tap controller and will run at a rate determined by the tap test clock. the clocking of the bist will be taken care of external to the af. this can be done by multiplexing the normal af clock with the test clock during the runbist instruction. the af bist implementation shall not require a seed value to be serially shifted in. the minimum number of test clock cycles necessary for the completion of bist needs to be provided. after the minimum number of clock cycles the af must hold the results of the bist constant until requested to shift them out by the tap controller. each execution of bist shall provide the same result and shall not depend on the state of signals received at non-tap interface signal. the serial bist operation is begun when the tl_bistena signal from the tap controller is asserted. this signal must remain asserted for the minimum duration speci- fied to guarantee a valid signature. when the minimum number of clock cycles has passed the tl_bistena signal will be de-asserted and a short time later the tl_bistse signal will be asserted to shift out the contents of the signature register through the af_tdo output. when the tl_bistena signal becomes de-asserted, the signature register should hold its content until the tl_bistena signal is asserted again, or the af is reset. if the minimum number of clock cycles for the completion of bist is not met, an intermediate signature will be obtained. this can be used to aid in fault isolation for internal manufacturing testing. node processor interface access to bist through the node processor interface is provided for board and system level testing. bist is initiated through this interface by writing the run bist instruction to the afcmd register. the bistdone and done bits in the afstat register are cleared upon issuing this instruction and the bist state machine moves from the idle to the operational state. at the completion of self test, the bistdone and done bits will be set in the afstat register. the done bit can be used to generate an interrupt to the node processor indicating the completion of the self test. the result of the self test can be obtained by reading the afbist register and comparing it to the known good signature.
p r e l i m i n a r y amd 63 supernet 3 bist pattern requirements this section presents the pattern requirements that the bist implementation should try to meet. the implemen- tation should try to meet as many of the requirements as possible, however, overhead considerations may make this goal unattainable. in the case that the requirements are not met, a means of applying these patterns functionally must be found. the functional application of patterns may dictate additional testability requirements in the af. the pattern requirements are divided into two sections, the first deals with the testing of the portion of the af that is sram-like, the second deals with the testing of the remaining af logic such as the match logic, priority encoder, exact logic, etc. pattern requirements for the sram-like portion of the af the following pattern requirements are taken from a paper by jain and stroud. some of the requirements may be architecture specific and may not be necessary. additional requirements may be necessary depending on the architecture of the af. this paper describes two algorithms that may be used in the implementation of the bist test. 1. each cell must undergo a 0_1 transition and then a 1_0 transition or vice versa. each cell must be read after each transition. 2. for every pair of physically adjacent cell i and j the test writes cell i with and 1 and cell j with a 0 and then cell i with a 0 and cell j with a 1. it then reads after each write. to consider coupling faults between master/slave bits, cells i and j are written with the same data. 3. each cell must be read twice after writing a 1 and a 0. 4. decoder faults should be detected by writing unique data in every memory word and then reading the af. 5. a special sequence of data patterns should be written and read to detect stuck-at faults in the read column decoder logic. 6. some memory words should be written and read with data having different logic values on every pair of adjacent input data lines. pattern requirements for the non-sram portion of the af the following pattern requirements may be difficult to implement in silicon and may have to be applied func- tionally. some of the patterns described in this section can be applied at the same time as the sram tests are being applied. the non-sram portion of the af consists of the comparator, the source address exact/inexact match logic, the destination exact/inexact match logic, and the multiple match logic (which includes the priority encoder logic). the stuck-at fault model is the only fault model used in developing the pattern requirements for this portion of the af. the other fault models discussed earlier were developed for memory arrays and it would not make sense to try to apply them to this section of the af. comparator the output of the comparator logic is the 32 match lines for each af entry. the output of the comparator is further modified by the state of the personality bits. the comparator can be viewed as 32 48-bit wide com- parators with one half of the inputs to each comparator supplied by the corresponding mask and data bits for each comparator, and the other half of the inputs to each comparator supplied by the comparand register. for the purpose of describing the data patterns necessary to test each comparator it will be assumed that all valid bits are set, all skip bits are reset and that either the sa or da bits are set to allow a match operation to be visible outside the af. the following table summarizes the truth table for a single bit of the comparator: table 1. truth table for the comparator mask data comp match 0 x x yes 100yes 101no 110no 111yes
amd p r e l i m i n a r y 64 supernet 3 1. the stuck-at 1 (s@1) condition in the mask bits for a comparator can be checked by first writing all mask bits to 0s, all data bits to 0s and the comparand register to all 1s. if any single mask bit is s@1, no match will occur otherwise a match will result as can be seen from the first line of table 1. to speed the testing for this condition, all entries can be tested in parallel if an all match indication is provided. all mask and data bits are written with 0s and compared simultaneously with the comparand. each entry should match resulting in the all match condition. if any mask bit is s@1, the all match condition will not occur and the fault can be detected. 2. the stuck-at 0 (s@0) condition in the mask bits for a comparator are tested by the data patterns shown in the third and fourth lines of table 1. these lines are a subset of the patterns needed to test the xnor faults that are represented by lines 2 through 5 of table 1. the outputs of the xnor gates for each bit are all anded together to form the match output of the comparator. the following test description will cover all stuck-at faults for the remainder of the comparator logic. these tests assume that all mask bits are written with 1s and assume the existence of an all match indication. the test is described in two parts: part #1 a) write each data entry with all 0s. b) write the comparand register with all 0s. c) perform a match operationshould get an all match indication. d) repeat steps a through c but this time use all 1s. at this point half of the xnor tests (lines 2 and 5 in table 1) have been completed and the and circuitry has been tested for s@0 faults. part #2 a) write each data entry with all 0s. b) do 48 matches while walking a 1 through a field of 0s in the comparand register. since a single bit is in error for each match, a match condition should never occur. c) repeat steps a and b with each data entry being all 1s and walking a 0 through a field of 1s in the comparand. at this point, all the xnor tests are completed. this also checks for s@1 faults in the and circuitry since all but a single bit match. this test also tests for the mask bit s@0. source address exact/inexact logic: the sram portion of this logic, namely the storage for the sa and sax personality bits will be tested by the sram tests presented earlier. what remains to be tested is the logic that generates the source address match and the source address match exact logic. the test pattern description that follows does not yet take into account the impact of the skip bit since its use hasnt been completely determined as yet. the patterns also assume the existence of an all match indication as described earlier. the following table summarizes the patterns that need to be applied to check each entry match and exact indicators: table 2. patterns necessary for match and exact indicators sax valid sa match[i] exact[i] all match? 11 11 1 yes 01 11 0 yes 10 10 0 no 11 00 0 no the individual match lines for each entry must be ord together to determine if a match has occurred. the indi- vidual exact match lines must also be ord together to determine if an exact match has occurred. the pattern shown in the first line of the table will detect all s@0 faults on the logic that generates each match and exact line for an entry. it will also check for a s@0 fault on the final match and exact outputs. the pattern shown in the second line of the table will check for all s@1 faults aris- ing from the sax personality bits and will also detect a s@1 fault on the final exact output. the pattern shown in the third line of the table will check for s@1 faults on the valid personality bits as well as on the final match and exact outputs. the final pattern shown in the fourth line of the table will check for s@1 faults on the sa personal- ity bits as well as on the final match and exact outputs. one could argue that the first pattern is not sufficient to cover all possible s@0 faults in the final oring of the individual match and exact lines since these faults are detected on the assumption of the existence of an all match indication (an all exact indication is also neces- sary). the all match indicator is used to speed the testing of the af since all entries can be written with the same values. if someone is uncomfortable with this potential loss in coverage, then an additional 32 patterns are needed that only apply the first pattern of the table to each entry by itself so that only one entry
p r e l i m i n a r y amd 65 supernet 3 causes the match and exact lines to be asserted. this pattern will take much longer to apply than the minimal set presented in table 2. destination address exact/inexact logic: since the destination address matching logic is identical to the source address matching logic, the same test can be applied as described in the previous section of this document. these tests can be applied simultaneously with the source address patterns. programming methods this section provides details of how the af is intended to be used. this section provides a description of the methods to write entries into the af, to find entries in the af and to invalidate entries in the af. writing entries into the af in order for the af to perform the function of matching addresses in network frames, the desired addresses must be loaded into the cam portion of the af. the following procedure should be followed to accomplish this operation. 1. write the comparand value into the np comparand registers. note that the comparand register will retain any previous value if it is not overwritten. 2. write the np mask register if it is desired to mask any portion of the comparand. note that the mask register will retain any previous value if it is not overwritten. 3. write the np personality register with the desired configuration of the sa, sax, da and dax bits. the valid bit must be set if this entry is to participate in any comparisons (either np or network). if the valid bit is not set, this entry may be overwritten when another entry is written to the cam. the skip bit should be cleared if this it will be necessary to find this entry through the np interface at a later time. note that the personality register will retain any previous value if it is not overwritten. 4. write the write cam instruction into the np command register. 5. the status register should be read once the done bit is set to ensure that the error bit was not set. note: the error bit in the status register will not be set if a write cam instruction is used when this bit is set. the user has to read this bit status before attempt- ing to write an entry into the cam. finding entries in the af once a number of entries are resident in the af, it may be necessary to find one or more of them. the process below should be used to perform this operation. 1. load the value of the comparand that it is desired to find into the np comparand register. 2. write the find instruction into the np command register. note: the comparand is not modified by the np mask registers. 3. read the np status register when the done bit is set. if the found bit is set, there is at least one matching entry in the af that does not have its skip bit set. if the mult bit is also set, there is more than one entry that matches the comparand that does not have the skip bit set. invalidating entries in the af in conjunction with managing the contents of the af, it may be required to remove entries. this process is called invalidation. to invalidate an entry in the af, the following steps should be followed. 1. load the np comparand register with the value of the af entry that is to be removed. 2. write the find instruction into the np command register. 3. when the done bit is set, read the np status register. do one of the following: 3a.if the found bit is not set, there is no entry in the af that matches the comparand that does not have its skip bit set. 3b.if the found bit is set and the mult bit is not set, there is only one entry in the af that matches the comparand that does not have its skip bit set. write the invalidate instruction into the np command register. 3c. if the found and mult bits are set, there is more than one entry in the af that matches the comparand that does not have its skip bit set. if all of these entries should be invalidated, write the invalidate instruction followed by the find instruction into the np command register repeatedly until the found bit is not set in the np status register. if only one of the multiple matching entries should be invalidated, write the read cam instruction to the np command register, compare the contents read back from the cam to the desired comparand, mask and personality. if the currently matching af entry is the one that should be invalidated, write the invalidate instruction to the np command register. if the currently matching af entry should not be invalidated, write the skip instruction to the np command register and repeat the invalidate process from the beginning. 4. write the clear all skip instruction to the np command register.
amd p r e l i m i n a r y 66 supernet 3 pdx functional discription introduction the pdx is a digital cmos core that is used in supernet 3. it employs new circuit techniques to achieve clock and data recovery. traditionally, phase-locked-loops (pll) are used for the purpose of clock recovery in data communication areas. there are both analog and digital versions of the pll components such as phase detector, filter, charge pump. a traditional pll always contains a voltage-con- trolled oscillator (vco) to regenerate a clock which is frequency synchronized to and phase aligned with the received data. the pdx employs techniques that are significantly different from the traditional pll. not only are the control functions completely digital, the vco function is also replaced by a proprietary delay-line technique. the result is a highly integratable core which can be manufactured in a standard digital cmos process. the pdx transmitter serializes encoded nrz symbols. the clock multiplier circuit generates a bit rate (125 mhz) clock from the lsclk reference. the serial data stream is converted into nrzi for output to the pmd transceiver. the pdx receiver uses the clock recovery circuit to extract clock information from the received data. the recovered clock is used to operate the serial-to-parallel conversion logic. pdx functional description the pdx accepts 4b5b encoded data symbols scram- ble or non-scrambled from the plc-s core at tdat 4C0 inputs. the 5-bit symbol is clocked into the pdx by the rising edge of lsclk, serialized, converted to nrzi format and shifted to the outputs. the tx+/txC pair carries pecl-compatible differential nrzi data to the fiber optic transmitter or to the twisted-pair transceiver interface. the pdx uses lsclk as the frequency reference to generate the serial link data rate. the external clock source must be crystal controlled and continuous. all of the internal logic of pdx runs on internal clocks that are derived from the external reference source or extracted from the received data. the pdxs clock multiplier is referenced to the rising edges of lsclk only. in order to generate the serial output waveforms conforming to the fddi specifications, the external reference clock must meet fddi frequency and stability requirements. under normal conditions, the frequency of lsclk must be within the fddi specified 50 ppm of the received data for the pdx to operate optimally. ( note: the 50 ppm is the tolerance of the crystal- controlled source. ) the tx+/txC serial outputs comply to the fddi smf-pmd jitter allocation and typically contains less than 0.4 ns peak-to-peak jitter at 125 mbaud. the pdx accepts encoded pecl nrzi signal levels at the rx+/rxC inputs and converts them to nrz format. the receiver circuit recovers data from the input stream by regenerating clocking information embedded in the serial stream. the pdx then clocks the unframed symbol (5 bits) to the rdat 4C0 interface on the falling edge of rsclk to the plc-s core. the pdx receiver uses advanced circuit techniques to extract embedded clock information from the serial input stream and recovers the data. its operating frequency is established by the reference at lsclk. the pdx is capable of tracking data correctly within 1000 ppm of lsclk (exceeds the frequency range defined by the fddi specification). fddi 4b5b encoding scheme ensures run-length limitation and adequate transition density of the encoded data stream, while tp-pmd achieves this on a statistical basis through data scrambling. the pdx clock recovery circuit is designed to meet and exceed a worst-case run-length tolerance of 60-bits in order to function correctly with both fiber-optic and twisted-pair pmds. the actual run-length tolerance is more than 1000 bits due to the unique data recovery technique. the pdx receiver has input jitter tolerance characteris- tics that meet or exceed the recommendations of physical layer medium dependent (pmd) fddi docu- ment. typically, at 125 mbaud (8 ns/bit), the peak-to- peak duty-cycle distortion (dcd) tolerance is 1.4 ns, the peak-to-peak data dependent jitter (ddj) toler- ance is 2.2 ns, and the peak-to-peak random jitter (rj) tolerance is 2.27 ns. the total combined peak-to-peak jitter tolerance is typically 5 ns with bit error rate (ber) better than 2.5 x 10 -10 .
p r e l i m i n a r y amd 67 supernet 3 default timer and register values the following are the default timer/register values on power-up reset. timer/register npaddr default value actual time value mir (1C0) register 12h & 13h 00 00 00 00h -na- tmax register 14h 03c7h 165.29664 ms tvx register and timer 15h 85h 3.4068 ms trt timer (bit 20C5) 16h 03c7h *1 165.29664 ms tht timer 17h ffffh *2 -na- tneg register (bit 20C5) 18h 03c7h 165.29664 ms tmrs register 19h 801fh -na- treq0 register 1ah 78e0h 165.29664 ms treq1 register 1bh 0000h *3 tpri(1C0) register 1c & 1d ffffh -na- tsync register 1fh 0000h -na- tmsync timer 40h fa97h *1 3.5456 ms (2xdmax when ring not operational) cmdreg1 00h 0000h -na- cmdreg2 01h 0000h -na- st1u 00h 0000h -na- st1l 01h 0007h -na- st2u 02h 4000h -na- st2l 03h 0000h -na- st3u 61h 4000h -na- st3l 62h 0000h -na- imsk1u 04h ffffh -na- imsk1l 05h ffffh -na- imsk2u 06h ffffh -na- imsk2l 07h ffffh -na- imsk3u 63h ffffh -na- imsk3l 64h ffffh -na- ivr 65h 0000h -na- imr 66h 0000h -na- said 08h 0000h -na- laim 09h 0000h -na- laic 0ah 0000h -na- lail 0bh 0000h -na- sagp 0ch 0000h -na- lagm 0dh 0000h -na- lagc 0eh 0000h -na- lagl 0fh 0000h -na-
amd p r e l i m i n a r y 68 supernet 3 timer/register npaddr default value actual time value mdreg1 10h 0080h -na- mdreg2 20h 8000h -na- mdreg3 60h 0000h -na- stmchn 11h xxx0 0000 0000 0000b bits 15, 14, 13 are for the revision number. fcntr 41h 0000h -na- lcntr 42h 0000h -na- ecntr 43h 0000h -na- fscntr 44h 0000h -na- eacb, earv1, eas, 22h, 23h, 24h, eaa0, eaa1, earv2 25h, 26h, 6bh unknown -na- sacl, sabc 28h & 29h unknown -na- rpr1, wpr1, swpr1 2dh, 2eh, 2fh unknown -na- rpr2, wpr2, swpr2 68h, 69h, 6ah unknown -na- wpxs, wpxa0, wpxa1 30h, 31h, 32h unknown -na- swpxs, swpxa0, swpxa1 34h, 35h, 36h unknown -na- rpxs, rpxa0, rpxa1 38h, 39h, 3ah unknown -na- marr, marw 3ch, 3dh unknown -na- wpxsf, rpxsf 2ah, 2bh unknown -na- frmthr 21h 0000h -na- notes: *1 lower 5 bits are all zero. *2 lower 5 bits are all one. *3 only lower 5 bits are valid.
p r e l i m i n a r y amd 69 supernet 3 supernet 3 registers supernet 3 programmable registers register mnemonic npaddr7C0 description cmdreg1 00 load the command register 1 instruction cmdreg2 01 load the command register 2 instruction st1u 00 upper 16 bits of status register 1 (read only) st1l 01 lower 16 bits of status register 1 (read only) st2u 02 upper 16 bits of status register 2 (read only) st2l 03 lower 16 bits of status register 2 (read only) imsk1u 04 upper 16 bits of imsk register 1 imsk1l 05 lower 16 bits of imsk register 1 imsk2u 06 upper 16 bits of imsk register 2 imsk2l 07 lower 16 bits of imsk register 2 said 08 short addressindividual laim 09 long address, individual (msw of laid) laic 0a long address, individual (middle of laid) lail 0b long address, individual (lsw of laid) sagp 0c short addressgroup lagm 0d long address, group (msw of lagp) lagc 0e long address, group (middle of lagp) lagl 0f long address, group (lsw of lagp) mod1 10 mode register 1 stmchn 11 state machine register mir1 12 upper 16 bitsmac information register (read only) mir0 13 lower 16 bitsmac information register (read only) tmax 14 tmax register tvx 15 tvx register trt 16 upper 16 bits of trt timer tht 17 upper 16 bits of tht timer tneg 18 upper 16 bits of tneg register tmrs 19 lower 5 bits of tneg, trt, tht timers bit 14C10lower 5 bits of tneg bit 9C5lower 5 bits of trt bit 4C0lower tht timer bit 15 is the late count treq0 1a stations lsw of requested trt treq1 1b stations msw of requested trt pri0 1c priority register for async0
amd p r e l i m i n a r y 70 supernet 3 supernet 3 programmable registers (continued) register mnemonic npaddr7C0 description pri1 1d priority register for async1 pri2 1e reserved tsync 1f tsync register mod2 20 mode register 2 frmthr 21 frame threshold register eacb 22 end address of claim/beacon area earv1 23 end address of receive queue eas 24 end address of synchronous queue eaa0 25 end address of asynchronous queue 0 eaa1 26 end address of asynchronous queue 1 eaa2 27 reserved sacl 28 start address of claim frame sabc 29 start address of beacon frame wpxsf 2a write pointer for special frames rpxsf 2b read pointer for special frames rpr1 2d read pointer for receive queue wpr1 2e write pointer for receive queue swpr1 2f shadow write pointer for receive queue wpxs 30 write pointer for synchronous queue wpxa0 31 write pointer for asynchronous queue 0 wpxa1 32 write pointer for synchronous queue 1 wpxa2 33 reserved swpxs 34 shadow write pointer for synchronous queue swpxa0 35 shadow write pointer for asynchronous queue 0 swpxa1 36 shadow write pointer for asynchronous queue 1 swpxa2 37 reserved rpxs 38 read pointer for synchronous queue rpxa0 39 read pointer for asynchronous queue 0 rpxa1 3a read pointer for asynchronous queue 1 rpxa2 3b reserved marr 3c memory read address register marw 3d memory write address register mdru 3e upper 16 bits of memory data register mdrl 3f lower 16 bits of memory data register tmsync 40 tmsync register
p r e l i m i n a r y amd 71 supernet 3 supernet 3 programmable registers (continued) register mnemonic npaddr7C0 description fcntr 41 frame counter lcntr 42 lost counter ecntr 43 error counter fscntr 44 frame strip counter frselreg 45 frame selection register 46 46 47 47 48 48 49 49 4a 4a 4b 4b 4c 4c 4d 4d 4e 4e 4f 4f 50l 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 59 59 5a 5a 5b 5b 5c 5c 5d 5d 5e 5e 5f 5f mdreg3 60 mode register 3 st3u 61 upper 16 bits of status register 3 (read only) st3l 62 lower 16 bits of status register 3 (read only) imsk3u 63 upper 16 bits of imsk register 3
amd p r e l i m i n a r y 72 supernet 3 supernet 3 programmable registers (continued) register mnemonic npaddr7C0 description imsk3l 64 lower 16 bits of imsk register 3 ivr 65 interrupt vector register (read only) imr 66 interrupt mask register ilr 67 (hidden) rpr2 68 read pointer for second receive queue wpr2 69 write pointer for second receive queue swpr2 6a shadow write pointer for second receive queue earv2 6b end address of receive 2 queue unlckdly 6c auto unlock delay register 6d 6d 6e 6e lwpr1 6f (hidden) lrwd1 70 (hidden) lwpr2 71 (hidden) lrwd2 72 (hidden) fifoflag 73 (hidden) 74 74 75 75 76 76 77 77 78 78 ltdpa1 79 last transmit descriptor pointer for async 1 queue lsa0 7a (hidden) lss 7b (hidden) 7c 7c 7d 7d 7e 7e 7f 7f plc_cntrl_a 80 plcCs control register a plc_cntrl_b 81 plcCs control register b intr_mask 82 plcCs interrupt mask register xmit_vector 83 plcCs transmit vector register vector_length 84 plcCs vector length register le_threshold 85 plcCs link error threshold register
p r e l i m i n a r y amd 73 supernet 3 supernet 3 programmable registers (continued) register mnemonic npaddr7C0 description c_min 86 plcCs connect state timer register tl_min 87 plcCs line state transmit timer register tb_min 88 plcCs break state timer register t_out 89 plcCs signalling timeout register plc_cntrl_c 8a plc_s control register c lc_length 8b plcCs link confidence test timer register t_scrub 8c plcCs scrub timer register ns_max 8d plcCs noise timer register tpc_load_value 8e plcCs tpc timer load register (write only) tne_load_value 8f plcCs tne timer load register (write only) plc_status_a 90 plcCs status register a (read only) plc_status_b 91 plcCs status register b tpc 92 plcCs tpc (read only) tne 93 plcCs tne (read only) clk_div 94 plcCs clk_div register (read only) bist_signature 95 plcCs bist signature (read only) rcv_vector 96 plcCs pcm receive vector register (read only) intr_event 97 plcCs interrupt event register (read only) viol_sym_ctr 98 plcCs violation symbol counter (read only) min_idle_ctr 99 plcCs minimum idle counter (read only) link_err_ctr 9a plcCs link error counter (read only) 9b C af reserved for future use afcmd b0 address filter command register afstat b2 address filter status register afbist b4 address filter bist signature afcomp2 b6 address filter comparand 2 register afcomp1 b8 address filter comparand 1 register afcomp0 ba address filter comparand 0 register afmask2 bc address filter mask 2 register afmask1 be address filter mask 1 register afmask0 c0 address filter mask 0 register afpers c2 address filter personality register c3 C cf reserved for future use
amd p r e l i m i n a r y 74 supernet 3 supernet 3 programmable registers (continued) register mnemonic npaddr7C0 description orstat d2 pdx status register d3Cdf reserved for future use
p r e l i m i n a r y amd 75 supernet 3 supernet 3 command registers supernet 3 command registers 1 instruction name code mnemonic software reset 01h load mdr from buffer memory with marr increment 02h irmemwi load mdr from buffer memory without marr increment 03h irmemwo idle/listen 04h claim/listen 05h beacon/listen 06h load tvx timer from tvx register 07h nonrestricted token mode 08h enter nonrestricted token mode 09h enter restricted token mode 0ah restricted token mode 0bh send unrestricted token 0ch send restricted token 0dh enter send-immediate mode 0eh exit send- immediate mode 0fh clear synchronous queue lock 11h clear asynchronous queue 0 lock 12h clear asynchronous queue 1 lock 14h reserved 18h clear receive queue 1 lock 20h clear receive queue 2 lock 21h tristate x bus (in sas only) 22h drive x bus 23h clear all queue locks 3fh supernet 3 command registers 2 instruction name code mnemonic reserved 01h reserved 02h reserved 04h reserved 08h abort current transmit activity 10h reset transmit queues 20h set tag bit 30h reserved 40h transmit command 50h
amd p r e l i m i n a r y 76 supernet 3 revision i.d. the bits 13, 14, 15 of the state machine register provides a three-bit binary value that indicates the revision number of the supernet 3. the revision i.d. shall be 111 for the first revision. the plc_status_a register, bit 15C11, provides a five-bit binary value that indicates the revision number of the plc-s block within the supernet 3. the revision i.d. shall be 01111. the afstat register, bit 7C5, provides a three-bit binary value that indicates the revision number of the address filter block. the revision i.d. shall be 111. the orstat register, bit 2C0, provides a three-bit binary value that indicates the revision number of the pdx block. the revision i.d. shall be 111. all other bits of orstat register are reserved.
p r e l i m i n a r y amd 77 supernet 3 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature 0 c to +70 c . . . . . . . . . . . . . . supply voltage referenced to v ss C0.3 v to +6.0 v . . . . . . . . . . . . . . dc voltage applied to any pin referenced to v ss C0.5 v to v cc + 0.5 v . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges temperature, t a 0 c to +70 c . . . . . . . . . . . . . . . . . . supply voltages, v cc +4.75 v to +5.25 v . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v il input low voltage 0.8 v v ih input high voltage 2.0 v v il input low voltage (note1) v cc C1.81 v cc C1.475 v v ih input high voltage (note 1) v cc C1.165 v cc C0.88 v i il input low current (note 9) v cc = maximum, v in = 0.5 v C200 m a i ih input high current (note 9) v cc = maximum, v in = 2.7 v C100 m a i oz output leakage current (note 10) 0.4 v < v out < v cc C10 10 m a v oh output high voltage (note 2) pecl load (note 3) v cc C1.025 v cc C0.6 v v ol output low voltage (note 2) pecl load (note 3) v cc C1.81 v cc C1.62 v v ol output low voltage i ol = maximum 0.4 v v oh output high voltage (note 4) i oh = Ci ol /2 2.4 v i ol output low current (note 5) 8.0 ma i ol output low current (note 6) 4.0 ma i oh output high current Ci ol / 2ma i oz output leakage current (note 7) 0.4 v < v out < v cc C10 10 m a i ix input leakage current (note 8) 0 v < v in < v cc C10 10 m a i cc power supply current v cc = maximum 400 ma notes: 1. applies to pecl inputs only rx+ ,rxC, sdi+,sdiC. 2. applies to pecl outputs only tx+,txC. 3. tested for v cc = minimum, shown limits are specified over entire v cc operating range. 4. v oh does not apply to open-drain pins ready , mintr [4:1]. 5. an i ol value of 8.0 ma applies to the following signals: addr[15:0], wr, rd , bd[31:0], bdp[3:0], bdtag, cso , mintr [4:1], and ready . 6. an i ol value of 4.0 ma applies to all signals except those listed in note 5. 7. i oz applies to all three-state output pins and bidirectional pins. 8. i ix applies to all non-pecl input-only pins. 9. i il , i ih applies to all ttl pins. 10. i oz applies to tdo.
amd p r e l i m i n a r y 78 supernet 3 key to switching waveforms ks000010 must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs
p r e l i m i n a r y amd 79 supernet 3 switching characteristics over commercial operating ranges clocks parameter no. symbol parameter description min max unit 1t per lsclk period 40 40 ns 2t pwh lsclk high pulse width 18 22 ns 3t pwl lsclk low pulse width 18 22 ns 4t per bclk period 80 80 ns 5t pwh bclk high pulse width 35 45 ns 6t pwl bclk low pulse width 35 45 ns 7t per bmclk period (bmclk tied to bclk) 80 80 ns 8t pwh bmclk high pulse width (bmclk tied to bclk) 35 45 ns 9t pwl bmclk low pulse width (bmclk tied to bclk) 35 45 ns 10 t per bmclk period (bmclk tied to lsclk) 40 40 ns 11 t pwh bmclk high pulse width (bmclk tied to lsclk) 18 22 ns 12 t pwl bmclk low pulse width (bmclk tied to lsclk) 18 22 ns 13 t sk bmclk to bclk skew (bmclk tied to bclk) 0 0 ns 14 t sk bmclk to lsclk skew (bmclk tied to lsclk) 0 0 ns 15 t sk lsclk to bclk skew 0 10 ns switching waveforms bclk 19574a-29 45 lsclk bmclk (bmclk tied to bclk) 10 11 12 1 23 bmclk (bmclk tied to lsclk) 15 6 13 78 9 14 figure 28. clock timings
amd p r e l i m i n a r y 80 supernet 3 switching characteristics over commercial operating ranges np parameter no. symbol parameter description min max unit 26 t s r/ w and npaddr[7:0] setup time to ds ( csi ) low 0 ns 27 t en ds ( csi ) low to npdata[15:0] enabled (asynchronous read) 0 28 t pd ds ( csi ) low to npdata[15:0] valid (asynchronous read) 275 ns 29 t s npdata[15:0] setup time before ready low (asynchronous read) 15 ns 30 t pd ds ( csi ) low to ready low 310 ns 31 t z ds ( csi ) high to ready deasserted 35 ns 32 t h r/ w and npaddr[7:0] hold time from ds ( csi ) high 0 ns 33 t inv npdata[15:0] invalid from ds ( csi ) high (asynchronous read) 5 34 t z ds ( csi ) high to npdata[15:0] deasserted 35 ns 35 t pwh ds high to ds low (asynchronous read/write recovery time) 100 ns 36 t s npdata[15:0] setup time to ds ( csi ) low (asynchronous write) C60 ns 37 t h npdata[15:0] hold time from ds ( csi ) high (asynchronous write) 0 ns 38 t s csi setup time to bclk 10 ns 39 t h csi hold time to bclk 10 ns 40 t s r/ w and npaddr[7:0] setup time to bclk 10 ns 41 t h r/ w and npaddr[7:0] hold time to bclk 10 ns 42 t z bclk to npdata[15:0] deasserted 30 ns 43 t en bclk to npdata[15:0] enabled 2 ns 44 t pd bclk to npdata[15:0] valid 30 ns 45 t inv bclk to npdata[15:0] invalid 2 ns 46 t s npdata[15:0] setup time to bclk 30 ns 47 t h npdata[15:0] hold time to bclk 20 ns 48 t pd bclk low to ready low 25 ns 49 t z bclk high to ready deasserted 35 ns 50 t pd bclk to mintr [4:1] valid 25 ns 51 t z bclk to mintr [4:1] deasserted 25 ns 52 t pwl rst pulse width low (20*t per 4) ns 53 t s npmemreq setup time to bmclk 15 ns 54 t h npmemreq hold time to bmclk 10 ns 55 t pd bmclk to npmemack high 20 ns 56 t pd bmclk to npmemack low 20 ns 57 t pd bmclk high to cso , rd , wr , addr15C0 disabled 30 ns
p r e l i m i n a r y amd 81 supernet 3 switching waveforms ds csi r/ w npaddr npdata ready 34 33 31 30 27 notes: 1. 26, 27, 28, and 30 are measured from csi or ds whichever goes low last. 2. 31, 33, 34, and 32 are measured from csi or ds whichever goes high first. open drain 28 29 35 26 19574a-30 note 2 note 1 27 32 26 figure 29. np asynchronous read
amd p r e l i m i n a r y 82 supernet 3 switching waveforms ds csi r/ w npaddr npdata ready 37 31 30 36 notes: 1. 26, 36, and 30 are measured from csi or ds whichever goes low last. 2. 31, 32, and 37 are measured from csi or ds whichever goes high first. open drain 35 26 19574a-31 note 2 note 1 27 32 26 figure 30. np asynchronous write
p r e l i m i n a r y amd 83 supernet 3 switching waveforms bclk csi r/ w npaddr npdata ready open drain 4 5 19574a-32 6 38 39 39 38 41 40 41 40 44 42 45 47 46 42 42 43 48 49 open drain 48 49 note: 1. ds is ignored in synchronous mode and should be inactive (high) during all synchronous accesses. figure 31. np synchronous read and write except mdr accesses
amd p r e l i m i n a r y 84 supernet 3 bclk csi r/ w npaddr npdata ready open drain 4 5 19574a-33 6 38 39 39 38 41 40 41 40 44 42 45 47 46 42 42 43 48 49 open drain 48 49 notes: 1. ds is ignored in synchronous mode and should be inactive (high) during all synchronous accesses. 2. read and write cycles could extend beyond two clock cycles. figure 32. np synchronous read and write mdr accesses
p r e l i m i n a r y amd 85 supernet 3 switching waveforms bmclk npmemreq npmemack cso rd wr addr 19574a-34 4 54 56 53 55 57 57 57 57 6 5 figure 33. np dma signals
amd p r e l i m i n a r y 86 supernet 3 switching waveforms 51 open drain 19574a-35 4 bmclk mintr [4:1] rst 50 5 6 52 figure 34. np miscellaneous signals
p r e l i m i n a r y amd 87 supernet 3 switching characteristics over commercial operating ranges host interface & buffer memory parameter no. symbol parameter description min max unit 76 t s hsreq2C0 setup time to bmclk high 15 ns 77 t h hsreq2C0 hold time to bmclk high 5 ns 78 t pd bmclk high to hsack high 25 ns 79 t pd bmclk high to hsack low 25 ns 80 t pd bmclk high to rdata high 25 ns 81 t pd bmclk high to rdata low 25 ns 82 t pd bmclk high to qcntrl2C0 valid 25 ns 83 t pd qcntrl2C0 invalid from bmclk high 5 ns 84 t pd bmclk high to addr 15C0 enabled 0 ns 85 t pd bmclk high to addr 15C0 valid 27 ns 86 t pd bmclk high to cso low 26 ns 87 t pd bmclk low to rd low 22 ns 88 t s bd 31:0, bdp 3:0, bdtag setup time to rd high 10 ns 89 t h bd 31:0, bdp 3:0, bdtag hold time from rd high 0 ns 90 reserved ns 91 t pd cso invalid from rd or wr high 0 ns 92 t pd addr 15:0 invalid from rd or wr high 4 ns 93 t pd bmclk low to wr low 18 ns 94 t s addr 15:0 valid to wr low setup time 0 ns 95 t pd bmclk low to bd 31:0, bdp 3:0, bdtag enabled 0 ns 96 t pd bmclk low to bd 31:0, bdp 3:0, bdtag valid 26 ns 97 t pd bd 31:0, bdp 3:0, bdtag valid before wr high 15 ns 98 reserved ns 99 t pd bd 31:0, bdp 3:0, bdtag invalid from wr high 0 ns 100 t pd bmclk high to bd 31:0, bdp 3:0, bdtag disabled 30 ns 121 t pd read pulse width 38 43 ns 122 t pd write pulse width 37 ns 123 t s addr 15:0 valid to rd low setup time 7 14 ns
amd p r e l i m i n a r y 88 supernet 3 switching waveforms bmclk hsreq hsack addr15C0 cso rd or wr rdata qctrl2C0 19574a-36 77 76 79 78 84 85 86 92 91 122 87 80 81 83 82 93 121 123 figure 35. host interface signal timings
p r e l i m i n a r y amd 89 supernet 3 switching waveforms bmclk addr15-0 cso rd bd31-0, bdp3-0, bdtag 19574a-37 84 91 92 85 86 88 89 121 87 figure 36. buffer memory read cycle timings bmclk addr15-0 cso wr bd31-0, bdp3-0, bdtag 19574a-38 84 91 92 85 86 97 99 122 93 100 94 96 95 figure 37. buffer memory write cycle timings
amd p r e l i m i n a r y 90 supernet 3 switching characteristics over commercial operating ranges external phy interface timing parameter no. symbol parameter description min max unit 126 t pd bclk high to xCbus (x0C7, xcu, xcl) valid 35 ns 127 t pd xCbus (x0C7, xcu, xcl) invalid from bclk high 6 ns 130 t s r0C7, rcu, rcl setup time to lsclk low 10 ns 131 t h r0C7, rcu, rcl hold time to lsclk low 5 ns switching waveforms lsclk r-bus (r0Cr7, rcu, rcl) x-bus (x0Cx7, xcu, xcl) 19574a-39 bclk 127 130 131 126 figure 38. phy interface timings
p r e l i m i n a r y amd 91 supernet 3 switching characteristics over commercial operating ranges mac miscellaneous signal timing parameter no. symbol parameter description min max unit 140 t s flxi/xmtinh setup time to bclk high 30 ns 141 t h flxi/xmtinh hold time from bclk high 5 ns 142 t pd bclk high to rs5C0, xs3C0 valid 35 ns 143 t pd rs5C0, xs3C0 invalid from bclk high 5 ns 144 t s xsamat , xdamat , xsa_xact , xda_xact setup time to bclk high 20 ns 145 t h xsamat , xdamat , xsa_xact , xda_xact hold time from bclk high 5 ns switching waveforms bclk flxi rs5C0 xs3C0 xsamat xdamat xsa_xact xda_xact 19574a-40 141 140 142 143 145 144 figure 39. mac miscellaneous signal timings
amd p r e l i m i n a r y 92 supernet 3 switching characteristics over commercial operating ranges external cam interface timing parameter no. symbol parameter description min max unit 156 t pd bclk high to rxafu3C0, rxafl3C0, rxafcu, rxafcl valid 25 ns 157 t pd rxafu3C0, rxafl3C0, rxafcu, rxafcl invalid from bclk high 0 ns switching waveforms bclk rxaf bus (rxafu0Crxafu3, rxafl0Crxafl3, rxafcu, rxafcl) 19574a-41 156 157 figure 40. external cam interface timings
p r e l i m i n a r y amd 93 supernet 3 switching characteristics over commercial operating ranges phy miscellaneous signal timing parameter no. symbol parameter description min max unit 200 t pd fotoff , lsr 2C0, ulsb, ebferr valid from bclk high 25 ns 201 t pd fotoff , lsr 2C0, ulsb, ebferr invalid from bclk high 0 ns 210 t s encoff setup time to bclk high 15 ns 211 t h encoff hold time from bclk high 10 ns switching waveforms bclk fotoff lsr 2C0, ulsb, ebferr 19574a-42 201 encoff 211 210 200 figure 41. phy miscellaneous signal timings
amd p r e l i m i n a r y 94 supernet 3 switching characteristics over commercial operating ranges test interface signal timing parameter no. symbol parameter description min max unit 226 t per tclk period 80 1000 ns 227 t pwh tclk pulse width high 45% 55% 228 t pwl tclk pulse width low 45% 55% 229 t s tdi, tms, trst setup time to tclk high 25 ns 230 t h tdi, tms, trst hold time from tclk high 6 ns 231 t inv tdo invalid from tclk low 0 ns 232 t pd tdo valid from tclk low 30 ns switching waveforms tclk tdo 19574a-43 231 tdi, tms trst 230 229 226 227 228 232 figure 42. test interface signal timings
p r e l i m i n a r y amd 95 supernet 3 switching characteristics over commercial operating ranges pmd interface signal timing parameter no. symbol parameter description test conditions min max unit 250 t r = tx+, txC rise time pecl load 0.3 3 ns 251 t f = tx+, txC fall time pecl load 0.3 3 ns 252 t sk = tx+ to txC skew pecl load 200 ps 253 t s sdi setup time to lsclk high 7 ns 254 t h sdi hold time from lsclk high 5 ns note: = : not included in the production test. tx+, txC txC 19574a-44 sdi 254 lsclk tx+ 251 80% 20% v ol v ol 252 1 253 v oh 250 figure 43. pmd interface signal timings
amd p r e l i m i n a r y 96 supernet 3 references phy device 1] amd am79c864a in the supernet 2 family for fddi , publication no. 15502, rev. c, physical layer controller with scrambler/ descrambler (plc-s). 2] ansi x3.148-1988, fddi physical layer specification. 3] ansi x3t9 smt ver. 7.2, station management specification. mac device 1] amd am79c830a formac plus datasheet in the supernet 2 family for fddi , publication no. 15502, rev. c. 2] ansi x3.139-1987, fddi media access control specification. testability ieee standard test access port and boundary-scan architecture , ieee standard 1149.1-1990 (approved feb. 15, 1990)
p r e l i m i n a r y amd 97 supernet 3 physical dimensions* pqr208, trimmed and formed 208-pin plastic quad flat pack (measured in millimeters) *for reference only. bsc is an ansi standard for basic space centering. trademarks copyright ? 1995 advanced micro devices, inc. all rights reserved. supernet, amd and the amd logo are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. pin 208 pin 104 pin 52 pin 1 i.d. 30.40 30.80 25.50 ref 27.90 28.10 25.50 ref 27.90 28.10 30.40 30.80 0.25 min 3.20 3.60 0.50 basic 3.95 max seating plane 16-038-pqr-2 pqr208 da92 7-20-94 ae pin 156

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